TNETX3100 datasheet(15/80 Pages) TI1

15 / 80 page

TNETX3100

ThunderSWITCH™ 10-PORT 10-/100-MBIT/S ETHERNET™ SWITCH

SPWS031D – JUNE 1997 – REVISED OCTOBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

data transmission

transmit control

Transmit control is partitioned into two blocks:

The frame control block handles the output of data into the PHYs, and a number of error states are handled.

If a collision is detected, the state machine jams the output. If the collision is late (after the first 64-byte buffer

has been transmitted) the frame is lost. If it is an early collision, the controller backs off before retrying. While

operating in full duplex, both carrier-sense (CRS) mode and collision-sensing modes are disabled.

The FIFO control block handles the flow of data from the FIFO buffers to the MAC interface for transmission.

The data within a FIFO buffer is cleared only after the data has been successfully transmitted without

collision (for the half-duplex ports). Transmission recovery also is handled in this state machine. If a collision

is detected, frame recovery and retransmission are initiated.

transmit pacing

When transmit pacing is enabled, the ThunderSWITCH architecture is capable of altering its transmission

routine during times of heavy network activity. The TNETX3100 is intelligent enough to sense heavy network

traffic and alter its transmission routing by intentionally inserting an extra amount of delay between transmission

attempts. The added delay reduces collision rates, and thus reduces the number of transmission attempts,

which helps reduce CPU utilization, lighten overall network traffic, and allows the network time to stabilize before

attempting transmission. If the delay was not added, the TNETX3100 would attempt to transmit on an already

heavily loaded network, adding to the network traffic’s unsuccessful transmission attempts.

Each Ethernet MAC incorporates transmit-pacing logic. This is enabled on an individual basis by setting the

TXPACE bit (bit 1) of the port control registers. When set, the MACs use transmit pacing to enhance

performance (when connected on networks using other transmit-pacing capable MACs). Transmit pacing

introduces delays into the normal transmission of frames, which delays transmission attempts between stations,

reducing the probability of collisions occurring during heavy traffic (as indicated by frame deferrals and

collisions). This increases the chance of successful transmission.

With pacing enabled, a frame is permitted (after one IPG) to immediately attempt transmission only if the pacing

counter is zero. If the pacing counter is nonzero, the frame is delayed by the pacing delay (a delay of

approximately four interframe gap delays).

interframe gap enforcement

The measurement reference for the interframe gap of 9.6

µs (when transmitting at 10 Mbit/s) is changed,

depending on frame traffic conditions. If a frame is successfully transmitted (without collision), 9.6

µs is

measured from MXXTXEN. If the frame suffered a collision, 9.6

µs is measured from MXXCRS. The

TNETX3100 can receive frames with an interframe gap of less than 9.6

µs and it always transmits its frames

with an interframe gap of 9.6

µs. The 100-Mbit/s ports can receive frames with an interframe gap of less than

0.96

µs and always transmit frames with a minimum interframe gap of 0.96 µs.

backoff

The TNETX3100 implements the IEEE Std 802.3 binary exponential backoff algorithm.

100-Mbit/s MAC interfaces (port 00)

The TNETX3100 allows port 00 to support pretagging and posttagging when forwarding frames to an external

routing engine. Posttagging is used by an external routing engine to provide destination port information to the

TNETX3100.

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