TNETX3100 datasheet(23/80 Pages) TI1

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TNETX3100

ThunderSWITCH™ 10-PORT 10-/100-MBIT/S ETHERNET™ SWITCH

SPWS031D – JUNE 1997 – REVISED OCTOBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

VLAN support

When EAM15 (mode select) is low, the EAM09–EAM00 inputs provide a mechanism for the EAM interface to

specify which destination port or group of destination ports is used to transmit the frame. Each signal represents

one destination port. Asserting one signal sends the frame to one destination port and asserting multiple signals

transmits the same frame to multiple ports. When using an external address/VLAN engine, the external VLAN

engine controls the EAM interface and the TNETX3100 forwards broadcast/multicast traffic to the configured

VLAN ports. This mode of operation employs the broadcast mechanism and appends the frames to the transmit

queues of the destination ports. The broadcast mechanism is an inefficient way to send frames to single ports

when individual port codes can be used.

For the internal address mode, the TNETX3100 provides one VLAN register per port. Each register contains

a bit map to indicate the VLAN group for the port. All broadcast/multicast traffic received on that port is then sent

only to the ports that are a part of the same VLAN.

DIO interface

The DIO interface allows host access to the TNETX3100. The DIO interface provides access to the on-chip

registers and statistics.

The DIO provides the following information:

D Network statistics counters – provide access to the network statistics information compiled in the statistics

RAM.

D System configuration registers – set or change the operation of the TNETX3100.

D RAM access – permits test access, allowing functional testing.

D Port registers – access port control, port status, and port address registers, permitting port management

and status interrogation.

To reduce design overheads and to simplify interface logic, a byte-wide asynchronous interface is defined. Ac-

cess to the internal TNETX3100 registers is available, indirectly, via the TNETX3100 host registers (see

host

registers for more detail). The four host registers are addressed directly from DIO interface address lines SAD1

and SAD0 (see Table 4).

Table 4. SAD1 and SAD0 Address Lines

SAD1

SAD0

DESCRIPTION

DIO address low

DIO address high

DIO data

DIO data increment

TNETX3100 数据表(PDF) 23 Page - Texas Instruments

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