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TNETX3100 数据表(PDF) 38 Page - Texas Instruments |
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TNETX3100 数据表(HTML) 38 Page - Texas Instruments |
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38 / 80 page ![]() TNETX3100 ThunderSWITCH™ 10-PORT 10-/100-MBIT/S ETHERNET™ SWITCH SPWS031D – JUNE 1997 – REVISED OCTOBER 1997 38 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DRAM test-access operation +3 +2 +1 +0 DIO ADDRESS DRAM data 0x00D4–0x00D7 DRAM addr DRAM flag 0x00D8–0x00DB INIST PACTST DIATST Reserved 0x00DC–0x00DF The user can write and read a repeating DRAM test by using the following procedure. • Soft reset the TNETX3150 (do not set the start bit). Perform the following: DIO write (address 00D3) = 80 DIO write (address 00D3) = 00 • Write to the port 00 TX FIFO block (72 bytes total): DIO write (address C200) = A5 DIO write (address C201) = A5 DIO write (address C202) = A5 DIO write (address C203) = A5 DIO write (address C204) = A5 DIO write (address C205) = A5 DIO write (address C206) = A5 DIO write (address C207) = A5 DIO write (address C208) = A5 • The FIFO can be filled by writing to the following offset: DIO write [address C208 + (10 * n)] = A5 where n = 0–7 • Write the DRAM forward pointer, flag,and DRAM address: DIO write (address 00D4) = FF ;Forward pointer least-significant bit DIO write (address 00D5) = FF ;Forward pointer DIO write (address 00D6) = FF ;Forward pointer DIO write (address 00D7) = FF ;Forward pointer most-significant bit DIO write (address 00D8) = xF ;Flag DIO write (address 00D9) = 00 ;DRAM address least-significant bit DIO write (address 00DA) = 00 ;DRAM address DIO write (address 00DB) = 80 ;DRAM address most-significant bit • The DRAM access occurs after the high byte (location 00DB) of the DRAM_address register is completed. To verify the DRAM access is complete, read the DRAMACT bit within the DRAM flag register: DIO read (address 00D8) = 8x DMA transfer not complete DIO read (address 00D8) = 0x DMA transfer complete |
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