TNETX3100 datasheet(63/80 Pages) TI1

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TNETX3100

ThunderSWITCH™ 10-PORT 10-/100-MBIT/S ETHERNET™ SWITCH

SPWS031D – JUNE 1997 – REVISED OCTOBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

timing requirements (see Notes 8 and 9 and Figure 16)

DRAM CAS-before-RAS (CBR) refresh cycle

NO.

MIN

NOM

MAX

UNIT

tc(OSCIN)

Cycle time, OSCIN clock

tw(OSCINH)

Pulse duration, OSCIN high

tw(OSCINL)

Pulse duration, OSCIN low

Frequency drift, OSCIN clock

±50

ppm

NOTES:

8. All DRAM output signals are synchronous to the DREF clock.

9. The TNETX3100 produces a refresh request at a fixed rate of once every 10.22

µs. If a block transfer is underway, the refresh is

deferred.

operating characteristics over recommended operating conditions (see Notes 8 and 9 and

Figure 16)

DRAM CAS-before-RAS (CBR) refresh cycle (with DREF clock)

NO.

PARAMETER

MIN

TYP

MAX

UNIT

tc(DREF)†

Cycle time, DREF clock

td(DCAS)†

Delay time, from DREF

↑ to DCAS transition

td(DRAS)†

Delay time, from DREF

↑ to DRAS transition

td(DOE)†

Delay time, from DREF

↑ to DOE transition

td(DWE)†

Delay time, from DREF

↑ to DWE transition

† All DRAM terminals are specified to have less than a 7-ns variance at any temperature and voltage.

NOTES:

8. All DRAM output signals are synchronous to the DREF clock.

9. The TNETX3100 produces a refresh request at a fixed rate of once every 10.22

µs. If a block transfer is underway, the refresh is

deferred.

operating characteristics over recommended operating conditions (see Notes 9 and 10 and

Figure 16)

DRAM CAS-before-RAS (CBR) refresh cycle (with OSCIN clock)

NO.

PARAMETER

MIN

MAX

UNIT

td(DCAS)

Delay time, from OSCIN

↑ to DCAS transition

td(DRAS)

Delay time, from OSCIN

↑ to DRAS transition

td(DOE)

Delay time, from OSCIN

↑ to DOE transition

td(DWE)

Delay time, from OSCIN

↑ to DWE transition

NOTES:

9. The TNETX3100 produces a refresh request at a fixed rate of once every 10.22

µs. If a block transfer is underway, the refresh is

deferred.

10. All DRAM output signals are synchronous to the OSCIN clock. Figure 15 shows a single DRAM write (TNETX3100 forward pointer

update).

TNETX3100 数据表(PDF) 63 Page - Texas Instruments

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