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TNETX3100 数据表(PDF) 70 Page - Texas Instruments

部件名 TNETX3100
功能描述  ThunderSWITCHE 10-PORT 10-/100-MBIT/S ETHERNETE SWITCH
PDF  80 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

TNETX3100 数据表(HTML) 70 Page - Texas Instruments

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TNETX3100
ThunderSWITCH™ 10-PORT 10-/100-MBIT/S ETHERNET™ SWITCH
SPWS031D – JUNE 1997 – REVISED OCTOBER 1997
70
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
DIO read cycle
D TNETX3100 host-register address data is placed on address terminals SAD1–SAD0 and SRNW is held
high.
D After setup time, SCS is taken low, initiating the read cycle.
D After delay following SCS low, SDATA7–SDATA0 is released from the Z state.
D After delay following SCS low, SDATA7–SDATA0 is driven with valid data and SRDY is pulled low. The host
can access the data.
D SCS is taken high by the host upon completion of the cycle, causing SRDY to deassert, and SRDY is driven
high for one clock cycle before going to the Z state. SDATA7–SDATA0 also goes to the Z state.
timing requirements (see Note 12 and Figure 20)
read cycle DIO interface
NO.
MIN
MAX
UNIT
1
tw(SCS)
Pulse duration, SCS low
40
ns
2
tsu(SAD)
Setup time, SAD1–SAD0 valid before SCS
↓
0
ns
3
tsu(SRNW)
Setup time, SRNW high before SCS
↓
0
ns
NOTE 12: SRDY should be held high using an external pullup resistor to ensure correct system operation.
operating characteristics over recommended operating conditions (see Note 12 and Figure 20)
read cycle DIO interface
NO.
PARAMETER
MIN
MAX
UNIT
4
tw(SRDY)
Pulse duration, SRDY high
20
ns
5
td(SRNW)
Delay time, from SRDY
↓ to SRNW↓
0
ns
6
td(SAD)
Delay time, from SRDY
↓ to SAD1–SAD0 invalid
0
ns
7
td(SDATA)1
Delay time from SRDY
↓ to SDATA7–SDATA0 valid
3
ns
8
td(SDATA)2
Delay time from SCS
↑ to SDATA7–SDATA0 invalid
0
60
ns
9
td(SCS–SRDY)1
Delay time, SCS
↓ to SRDY↓
0
ns
10
td(SCS–SRDY)2
Delay time, SCS
↑ to SRDY↑
0
60
ns
NOTE 12: SRDY should be held high using an external pullup resistor to ensure correct system operation.
9
2
1
5
6
7
4
10
Address
Data
SCS
(input)
SRNW
(input)
SAD1–SAD0
(input)
SDATA7–SDATA0
(output)
SRDY
(output)
OSCIN
(input)
8
3
Z
Z
Figure 20. DIO Read Cycle



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