TNETX3100 datasheet(42/80 Pages) TI1

42 / 80 page

TNETX3100

ThunderSWITCH™ 10-PORT 10-/100-MBIT/S ETHERNET™ SWITCH

SPWS031D – JUNE 1997 – REVISED OCTOBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

DIO access to counter statistics

When accessing the statistics values from the DIO port, it is necessary to perform four 1-byte DIO reads to obtain

the full 32-bit counter. To prevent the counter being updated while reading the four bytes, the user should access

the low byte first, followed by the upper three bytes. On reading the low byte, the counter statistic value is

transferred to a 32-bit holding register before being placed on the DIO bus. The register is updated only when

reading the low byte of the counter statistic. When the counter statistics are accessed in this way, the user does

not see spurious updates.

The statistics, RX overrun, and collision registers are cleared only during a reset or when bit 4 (CLRSTS) of the

system control register at 0x00C3 is set. When the registers roll over, a rollover indication is not given.

clearing statistics counter memory

The statistics RAM can be requested to clear at any time during operation. This is achieved by setting the

CLRSTS bit in the system control register (DIO 0xC3). The state of this bit is latched. When set, the next statistics

update cycle writes 0 to all counters in the statistics RAM before resetting the latched bit. If the CLRSTS bit has

not subsequently been reset by the user, the latched bit is set again, causing the TNETX3100 to load 0 into the

statistics counters again. This continues until the CLRSTS bit is reset by the user. Soft reset has no effect on

the statistics counters (their contents are not cleared during a soft reset). A hard reset causes the statistics

counters to reset to 0. Port statistics cannot be cleared on a per-port basis.

queue structures address map at 0x86E0 – 0x20*N + 0x86FF – 0x20*N (N = port number in hex)

ADDRESS

Transmit queue N head

Transmit queue N tail

Transmit queue N length

0x86E0–(0x20*N)

Immediate queue N head

Immediate queue N tail

Immediate queue N length

0x86E8–(0x20*N)

Receive queue N head

Receive queue N tail

Receive queue N length

0x86F0–(0x20*N)

Reserved

0x86F8–(0x20*N)

EEPROM interface

The EEPROM interface is provided so that system-level manufacturers can optionally provide a preconfigured

system to their customers. Customers also can change or reconfigure their systems and retain their preferences

between system power downs.

The EEPROM contains configuration and initialization information, which is accessed infrequently (typically

power up and reset).

The TNETX3100 uses the 24C02 serial EEPROM device (2048 bits organized as 256 bits

× 8). See Table 7.

The 24C02 device uses a two-wire serial interface for communication and is available in a small-footprint

package.

The organization of the EEPROM data is the same format as the TNETX3100 registers 0x00–0xD7 (see section

on internal registers). This allows a complete initialization to be performed by downloading the contents of the

EEPROM into the TNETX3100. During the download, no DIO operations are permitted. The LOAD bit in the

system control registers cannot be set during a download, preventing a download loop. The LOAD bit is reset

after completion of the download.

The TNETX3100 detects the presence or absence of the EEPROM. If no EEPROM is installed, the EDIO

terminal should be tied low. For EEPROM operation, the terminal requires an external pullup (see EEPROM

data sheet). If no EEPROM is detected, the TNETX3100 assumes default modes of operation at power up.

Downloading the configuration from the EEPROM terminals is disabled when no EEPROM is present. The

timing information for the EEPROM interface is provided in Figure 23 and Figure 24.

If EEPROM is present, but has a bad CRC, the fault LED is illuminated.

TNETX3100 数据表(PDF) 42 Page - Texas Instruments

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