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TNETX3100 数据表(PDF) 26 Page - Texas Instruments |
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TNETX3100 数据表(HTML) 26 Page - Texas Instruments |
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26 / 80 page  TNETX3100 ThunderSWITCH™ 10-PORT 10-/100-MBIT/S ETHERNET™ SWITCH SPWS031D – JUNE 1997 – REVISED OCTOBER 1997 26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TNETX3100 condensed DIO memory map (continued) Table 5. TNETX3100 Condensed DIO Memory Map (Continued) DIO ADDRESS (BITS 15–0) SHOWN IN HEX FORMAT DESCRIPTION AREA OF TNETX3100 D400–D5FF Port 05 RX FIFO FIFO RAM D600–D7FF Port 05 TX FIFO FIFO RAM D800–D9FF Port 06 RX FIFO FIFO RAM DA00–DBFF Port 06 TX FIFO FIFO RAM DC00–DDFF Port 07 RX FIFO FIFO RAM DE00–DFFF Port 07 TX FIFO FIFO RAM E000–E1FF Port 08 RX FIFO FIFO RAM E200–E3FF Port 08 TX FIFO FIFO RAM E400–E5FF Port 09 RX FIFO FIFO RAM E600–E7FF Port 09 TX FIFO FIFO RAM E800–FFFF Reserved (not implemented) address registers at [0x08*(A–16)] + 0x0000 through [0x08*(A–16)] + 0x0007 (A = address register in hex, legal values are 16–31) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 (MSB) BIT 2 BIT 1 BIT 0 (LSB) DIO ADDRESS Reserved Reserved Reserved Reserved Reserved Reserved Reserved LOCK† 0x08(A-16) Reserved Reserved Reserved Reserved Port Number Port Number Port Number Port Number 0x08(A–16)+0x01 Address Bit 47 Address Bit 46 Address Bit 45 Address Bit 44 Address Bit 43 Address Bit 42 Address Bit 41 Address Bit 40 0x08(A–16)+0x02 Address Bit 39 Address Bit 38 Address Bit 37 Address Bit 36 Address Bit 35 Address Bit 34 Address Bit 33 Address Bit 32 0x08(A–16)+0x03 Address Bit 31 Address Bit 30 Address Bit 29 Address Bit 28 Address Bit 27 Address Bit 26 Address Bit 25 Address Bit 24 0x08(A–16)+0x04 Address Bit 23 Address Bit 22 Address Bit 21 Address Bit 20 Address Bit 19 Address Bit 18 Address Bit 17 Address Bit 16 0x08(A–16)+0x05 Address Bit 15 Address Bit 14 Address Bit 13 Address Bit 12 Address Bit 11 Address Bit 10 Address Bit 9 Address Bit 8 0x08(A–16)+0x06 Address Bit 7 Address Bit 6 Address Bit 5 Address Bit 4 Address Bit 3 Address Bit 2 Address Bit 1 Address Bit 0 0x08(A–16)+0x07 † LOCK is present for network address register 0; for all other network address registers (1–15), LOCK is reserved. address register description The 16 network registers shown are combined with the other 16 registers (address 0100 through 017F) for a total of 32 network address registers; they form a 32-deep push-down stack, and this stack holds the last 32 source addresses seen by the TNETX3100. When a frame is received by the TNETX3100, the source address is extracted and pushed onto the top of the stack (register 0) along with the source port number, and the current contents of the stack, pushed down one location. The oldest address that was at the bottom of the stack (register 31) is discarded. |
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