TNETX3100 datasheet(48/80 Pages) TI1

48 / 80 page

TNETX3100

ThunderSWITCH™ 10-PORT 10-/100-MBIT/S ETHERNET™ SWITCH

SPWS031D – JUNE 1997 – REVISED OCTOBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

FIFO RAM test access

FIFO RAM access for test is provided through the DIO interface. This allows full RAM access for RAM testing.

Access to the FIFO is allowed following a soft reset and before the START bit is written (or after power up and

before the START bit is written). The soft reset bit should be set, then immediately reset. If the soft reset bit is

not cleared, the TNETX3100 holds the DRAM refresh logic operation in reset and the contents of the external

memory become invalid.

To access the FIFO RAM from the DIO, bytes are written to a holding latch that is the width of the RAM word

(72 bits). When a byte is accessed, the whole word is updated in RAM. If the same pattern is loaded throughout

the memory, it requires only a new FIFO RAM address for setup between accesses on a single byte within the

word. The data in the latch does not change (i.e., a read /modify/write is not performed).

structure (statistics) RAM test access

Test access to the statistics RAM is provided through the DIO port after the TNETX3100 is soft reset (or following

power up before the start bit is set). In this mode, all locations of the RAM are written to and read from. Once

the start bit is set, only read access is permitted to the RAM. When asserting soft reset, it is important to reset

the soft reset bit immediately after setting it. This ensures that the DRAM refresh logic operation is not held at

reset. If held at reset, normal DRAM refreshes fail to occur, resulting in the DRAM contents becoming invalid.

To access the structure RAM from the DIO, bytes are written to a holding latch that is the width of the RAM word

(64 bits). When a byte is accessed, the whole word is updated in RAM. If the same pattern is loaded throughout

the memory, it only requires a new structure RAM address for set up between accesses on a single byte within

the word. The data in the latch does not change (i.e., a read/modify/write is not performed).

internal frame-wrap test mode

The frame-wrap test mode allows the user to send a frame into a designated source port and selectively route

the frame to and from ports involved in the test (or return the frame directly) before retransmitting the frame on

the designated source port. By varying the number of ports between which the frame is forwarded, the potential

fault-capture area can be expanded or constrained. Initially, it is desirable to send data to and from each port

in turn, allowing the MAC-to-FIFO interface and MAC terminals to be tested for each port.

The TNETX3100 provides an internal-loopback test mode. Internal loopback allows the frame data path to be

tested, and is useful for individual die burn-in testing and system testing with minimal reliance on external parts.

Internal loopback is selected by suitably setting the INTWRAP field of the DIATST register (see

DIATST register

at 0x00DD). Port 00 (uplink) or port 09 can be selected as the source port for injecting frames into the

TNETX3100 when internal wrap is selected. All other ports are set to internally wrap frames (see Figure 11).

TNETX3100 数据表(PDF) 48 Page - Texas Instruments

TNETX3100 数据表(HTML) 48 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

数据表下载