TNETX3100 datasheet(71/80 Pages) TI1

71 / 80 page

TNETX3100

ThunderSWITCH™ 10-PORT 10-/100-MBIT/S ETHERNET™ SWITCH

SPWS031D – JUNE 1997 – REVISED OCTOBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

timing requirements (see Note 13 and Figure 21)

EAM interface101112

NO.

MIN

MAX

UNIT

tsu(EAM)

Setup time, EAM15–EAM0 valid before OSCIN

↑

th(EAM)

Hold time, EAM15–EAM0 valid after OSCIN

↑

NOTE 13: To determine the start of frame, the external address hardware tests bit 35 of the forward pointer and decodes the first flag nibble placed

on the DRAM data bus. Bit 35 should be 0, indicating a valid data-frame start as opposed to a link buffer transfer. By using the DCAS

signal, the destination address and source address of the frame is extracted for external processing.

The channel destination is returned in one of two methods. If only one port address is specified (effectively a unicast), the EAM15 (MODE

SELECT) signal is asserted, and a 5-bit port code is placed on EAM04–EAM00. If a group multicast is required, the channel bit map

is applied directly to the EAM interface with EAM15 (MODE SELECT) low. The EAM15–EAM0 signals must be valid by the start of the

15th memory access.

All signals in the external address checking interface are synchronous with the DREF clock.

VALID

OSCIN

(input)

DOE

(output)

DWE

(output)

DRAS

(output)

DCAS

(output)

ROW

Col

FPTR

Data

Col

Data

0PPP

01UU CCCC

00UU

1BBB

1SSS

CCCC

00UU

CCCC

00UU

DA7–DA0

DX2–DX0

(output)

DD31–DD0

(input/

output)

DD35–DD32

(input/

output)

EAM15–EAM0

(input)

Forward Pointer

Field

Low Nibble of

Start Flag

High Nibble of

Start Flag

EAM Code

Figure 21. EAM Interface Timing

600 ns

300 ns

LEDCLK

(output)

LEDSTR

(output)

LEDDATA

(output)

600 ns

S/W

FLOW

Port

FAULT

Figure 22. LED Interface Timing

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