TNETX3100 datasheet(35/80 Pages) TI1

35 / 80 page

TNETX3100

ThunderSWITCH™ 10-PORT 10-/100-MBIT/S ETHERNET™ SWITCH

SPWS031D – JUNE 1997 – REVISED OCTOBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

RAM size register at 0x00D2

BIT

MTEST

Reserved

FLOW

TAGON

RSIZE

Initial Values After Reset

BIT

NAME

FUNCTION

MTEST

Test access bit. Before DIO accesses are made to the DIO test registers (address range 0x00DC–0x00FF), the

user must write MTEST = 1. When an EEPROM is used to initialize registers 0x00–0xC3, MTEST is initialized to

0. MTEST allows access to the DIO registers to enable frame-wrap test modes.

Reserved

Reserved. Set to 0.

FLOW

Flow control enable bit. When FLOW = 1, the TNETX3100 implements collision-based flow control. When

FLOW = 0, no flow control is implemented.

TAGON

Post-frame tag enable bit. TAGON enables the requirement for post-frame tagging on the port 00 uplink. When

TAGON = 1, the TNETX3100 uses the posttag to route frames received on the uplink. The other 100 Mbit/s (port

01) does not support post-frame tagging. When TAGON = 0, the TNETX3100 uses either the EAM interface or the

internal address-lookup registers to route frames received on the uplink.

RAM size select. RSIZE indicates the size of the external DRAM and the number of 64-byte data buffers available.

This field is used by the TNETX3100 to determine how many buffers to initialize. The code values are:

BIT

CODE

NUMBER OF

VALUES

BUFFERS

0100

× 36

240

0101

× 36

480

0110

16K

× 36

960

RSIZE

0111

32K

× 36

1920

3–0

RSIZE

1000

64K

× 36

3840

1001

128K

× 36

7680

1010

256K

× 36

15 360

1011

512K

× 36

30 720

1100

× 36

61 440

1101

× 36

122 880

1110

× 36

245 760

1111

Reserved

—

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