TNETX3100 datasheet(28/80 Pages) TI1

28 / 80 page

TNETX3100

ThunderSWITCH™ 10-PORT 10-/100-MBIT/S ETHERNET™ SWITCH

SPWS031D – JUNE 1997 – REVISED OCTOBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

port-N control register at 0x2*N + 0080 (N = port number in hex)

RESET

INITIAL VALUES AFTER RESET†

CONDITIONS

BIT

DISABLE

ENABLE

STFORTX

STFORRX

NLEARN

MWIDTH

TXPACE

FORCEHD

Port 00

(initial value after reset)

Ports 01–09

(initial value after reset)

† This register is reset to initial values after any reset condition and must be reloaded.

BIT

NAME

FUNCTION

DISABLE

Port disable. DISABLE = 1 disables the port. Frames are not forwarded from or to a disabled port, but the port

attempts to transmit any previously queued frames.

Latched bit. DISABLE is set by both hard and soft reset (default state is port disabled). DISABLE is cleared by

writing ENABLE = 1.

ENABLE

Port enable. ENABLE = 1 enables the port, provided DISABLE = 1 is not written at the same time. Writing a 0 to

ENABLE has no effect. ENABLE is always read as 0.

STFORTX

Store and forward on transmission. Cut-through to this port is not allowed when STFORTX = 1.

STFORRX

Store and forward on receive. Cut-through from this port is disabled when STFORRX = 1.

NLEARN

Not learn. When NLEARN = 1, the port does not take part in address-learning activity. Any stored addresses remain

valid until they are aged out, and secured addresses are never aged out. When NLEARN = 0, the port takes part

in address-learning activity.

MWIDTH

MII width selection. MWIDTH is only valid on 10-/100-Mbit/s capable ports (ports 00, 01). When MWIDTH = 1, and

the port is operated in the 10-Mbit/s mode, the interface is operated in nibble-serial mode. When MWIDTH = 0, the

interface is operated in the bit-serial mode.

TXPACE

Transmit pacing. When TXPACE = 1, the port uses transmission pacing to enhance performance. When

TXPACE = 0, transmit pacing is disabled.

FORCEHD

Force half duplex. When FORCEHD = 1, the DUPLEX terminal is pulled down (active pulldown on the input), forcing

the PHY to operate in half-duplex mode.

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