TNETX3100 datasheet(69/80 Pages) TI1

69 / 80 page

TNETX3100

ThunderSWITCH™ 10-PORT 10-/100-MBIT/S ETHERNET™ SWITCH

SPWS031D – JUNE 1997 – REVISED OCTOBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

DIO write cycle

D TNETX3100 host-register address data SAD1–SAD0 and SDATA7–SDATA0 are asserted and SRNW is

taken low.

D After the setup time, SCS is taken low, initiating a write cycle.

D The TNET3100 pulls SRDY low as the data is accepted and SDATA7–SDATA0, SAD1–SAD0, and SRNW

are deasserted after the hold time is satisfied.

D SCS is taken high by the host to complete the cycle, causing SRDY to be deasserted, and SRDY is driven

high for one cycle before going to the high-impedance (Z) state.

timing requirements (see Note 11 and Figure 19)

write cycle DIO interface

NO.

MIN

MAX

UNIT

tw(SCS)

Pulse duration, SCS low

tsu(SAD)

Setup time, SAD1–SAD0 valid before SCS

↓

tsu(SDATA)

Setup time, SDATA7–SDATA0 valid before SCS

↓

tsu(SRNW)

Setup time, SRNW low before SCS

↓

NOTE 11: The DIO interface/DIO write cycle is asynchronous, allowing easy adaptation to a range of microprocessor devices and computer

system interfaces.

operating characteristics over recommended operating conditions (see Note 11 and Figure 19)

write cycle DIO interface

NO.

PARAMETER

MIN

MAX

UNIT

tw(SRDY)

Pulse duration, SRDY high

td(SRNW)

Delay time, from SRDY

↓ to SRNW↑

td(SAD)

Delay time, from SRDY

↓ to SAD1–SAD0 invalid

td(SDATA)

Delay time, from SRDY

↓ to SDATA7–SDATA0 invalid

td(SCS-SRDY)1

Delay time from SCS

↑ to SRDY↑

td(SCS-SRDY)2

Delay time from SCS

↓ to SRDY↓

NOTE 11: The DIO interface/DIO write cycle is asynchronous, allowing easy adaptation to a range of microprocessor devices and computer

system interfaces.

Address

Data

OSCIN

(input)

SCS

(input)

SRNW

(input)

SAD1–SAD0

(input)

SDATA7–SDATA0

(input)

SRDY

(output)

Figure 19. DIO Write Cycle

TNETX3100 数据表(PDF) 69 Page - Texas Instruments

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