| 数据搜索系统,热门电子元器件搜索 |
|
TNETX3100 数据表(PDF) 11 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
TNETX3100 数据表(HTML) 11 Page - Texas Instruments |
|
11 / 80 page ![]() TNETX3100 ThunderSWITCH™ 10-PORT 10-/100-MBIT/S ETHERNET™ SWITCH SPWS031D – JUNE 1997 – REVISED OCTOBER 1997 11 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions (Continued) EEPROM interface TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION ECLK 153 O EEPROM data clock. ECLK is the serial EEPROM clock and requires an external pullup resistor. EDIO 152 I/O EEPROM data input/output. EDIO is the serial EEPROM data I/O signal that requires an external pullup (see EEPROM data sheet) for EEPROM operation. Tying this terminal to ground disables the EEPROM interface and prevents auto-configuration. Reset is asynchronous, therefore, OSCIN needs to operate while RESET is active. LED activity interface TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION LEDCLK 129 O LED clock. LEDCLK is the serial-shift clock for the LED-status data. LEDDATA 128 O LED data. LEDDATA is the active-low serial data signal for the LED-status data. LEDSTR 124 O LED strobe. LEDSTR pulses latch the contents of the LED shift registers. JTAG interface TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION TCLK 148 I Test clock. TCLK clocks state information and test data into and out of the device during operation of the test port. TDI 149 I Test data input. TDI serially shifts test data and test instructions into the device during operation of the test port. TDO 150 O Test data out. TDO serially shifts test data and test instructions out of the device during operation of the test port. TMS 151 I Test mode select. TMS controls the state of the TNETX3100 test-port controller. TRST 147 I Test reset. TRST asynchronously resets the test-port controller. miscellaneous functions TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION DREF 125 O DRAM reference clock. OSCIN 127 I Oscillator input. OSCIN is the TNETX3100 clock input (50 MHz). RESET 146 I Reset. RESET (active low) resets the TNETX3100. RESET should be held low for 25 ms after the power supplies and clocks have stabilized. This input is synchronous and therefore, the system clock is operational during reset. |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |