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STA321 数据表(PDF) 150 Page - STMicroelectronics |
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STA321 数据表(HTML) 150 Page - STMicroelectronics |
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150 / 157 page ![]() I2C disabled (microless) mode STA321 150/157 Doc ID 15351 Rev 3 15 I2C disabled (microless) mode Figure 55. Microless mode block diagram In microless mode (I2CDIS = 1) the I2C interface is inhibited and SDA and SCL are used as static inputs. The device is working in the configuration shown in Figure 55 with the ADC connected to input line 1 and to SAI out. The processing chain uses the inputs from SAI input 1. The working modes are selected via the logical levels on the inputs SDA, SCL as follows: SCL = 0 : CMOS bridge outputs come from digital input serial audio interface; SCL = 1 : CMOS bridge outputs come from analog ADC input. SDA = 0 : external amplifier outputs come from digital input serial audio interface; SDA = 1 : external amplifier outputs come from analog ADC input. At power-up the channel volume is set to -60 dB. The volume is controlled by pulsing the inputs LRCLKO and BICLKO as follows: when pulsing LRCLKO = 1 and BICLKO = 1 simultaneously the channel volume is set to 0 dB. Any LRCLKO = 1 pulse causes a channel volume decrease of 0.5 dB. Any BICLKO = 1 pulse causes a channel volume increase of 0.5 dB. The channel volume change applies only to the external amplifier. The digital output serial audio interface is always fed with the result of the ADC conversion with no volume control (line-out mode). It is in master mode when SCL = 1 and SDA = 1 otherwise it is in slave mode. It is configured in I2S format. The LRCLK and BICLK signals are shared between input and output SAI. 4-channel sample rate converter Vol ctrl FFX™ modulator Input SAI Osc PLL Divider Output SAI CMOS bridge ADC V_BIAS VCM VHI VLO BICLKI1 LRCLKI1 SDATAI1 INL1 INR1 BICLKI2 LRCLKI2 SDATAI2 INL2 INR2 SDATAO1 EAPWM4 EAPWM3 EAPWM2 EAPWM1 OUT1 OUT2 OUT3 PWM00 EAFTN EATSN EAPDN |
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