ST7LITE20F2 datasheet(121/166 Pages) STMICROELECTRONICS

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Electrical characteristics

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Figure 52. fCPU maximum operating frequency versus V

DD supply voltage

13.3.2

Operating conditions with low voltage detector (LVD)

TA = -40 to 85°C, unless otherwise specified

Table 60.

General operating conditions

Symbol

Parameter

Conditions

Min

Max

Unit

VDD

Supply voltage

fCPU = 4 MHz. max.

2.4

5.5

fCPU = 8 MHz. max.

3.3

5.5

fCPU

CPU clock frequency

3.3 V

≤ VDD≤ 5.5 V

up to 8

MHz

2.4 V

≤ VDD<3.3 V

up to 4

fCPU [MHz]

SUPPLY VOLTAGE [V]

2.0

2.4

3.33.5

4.04.5

5.0

FUNCTIONALITY

NOT GUARANTEED

IN THIS AREA

5.5

FUNCTIONALITY

GUARANTEED

IN THIS AREA

(UNLESS OTHERWISE

STATED IN THE

TABLES OF

PARAMETRIC DATA)

2.7

Table 61.

Power on/power down operating conditions

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VIT+(LVD)

Reset release threshold

(VDD rise)

High Threshold

Med. Threshold

Low Threshold

4.00(1)

3.40(1)

2.65(1)

Not tested in production.

4.25

3.60

2.90

4.50

3.80

3.15

VIT-(LVD)

Reset generation threshold

(VDD fall)

High Threshold

Med. Threshold

Low Threshold

3.80

3.20

2.40

4.05

3.40

2.70

4.30(1)

3.65(1)

2.90(1)

Vhys

LVD voltage threshold

hysteresis

VIT+(LVD)-VIT-(LVD)

−

200

−

VtPOR

VDD rise time rate

(2)

Not tested in production. The VDD rise time rate condition is needed to insure a correct device power-on

and LVD reset. When the VDD slope is outside these values, the LVD may not ensure a proper reset of the

MCU.

Use of LVD with capacitive power supply: with this type of power supply, if power cuts occur in the

application, it is recommended to pull VDD down to 0 V to ensure optimum restart conditions. Refer to

circuit example in Figure 84: RESET pin protection when LVD is enabled

−

20000

μs/V

tg(VDD)

Filtered glitch delay on VDD

Not detected by the

LVD

−−

150

IDD(LVD) LVD/AVD current consumption

−−

220

−μA

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