ST7LITE20F2 datasheet(124/166 Pages) STMICROELECTRONICS

124 / 166 page

Electrical characteristics

ST7LITE20F2 ST7LITE25F2 ST7LITE29F2

124/166

Doc ID 8349 Rev 5

Figure 53. RC Osc Freq vs VDD @ TA= 25°C (calibrated with RCCR1: 3V @ 25°C)

Figure 54. RC Osc Freq vs VDD (calibrated with RCCR0: 5V@ 25°C)

Figure 55. Typical RC oscillator Accuracy vs temperature @ VDD=5V (calibrated with

RCCR0: 5V @ 25°C)

JITPLL

PLL jitter (

ΔfCPU/fCPU)

−−

1(6)

−

IDD(PLL) PLL current consumption

TA=25°C

−

190(2)

−μA

If the RC oscillator clock is selected, to improve clock stability and frequency accuracy, it is recommended to place a

decoupling capacitor, typically 100nF, between the VDD and VSS pins as close as possible to the ST7 device.

Data based on characterization results, not tested in production.

See Section 7.1: Internal RC oscillator adjustment.

After the LOCKED bit is set ACCPLL is max. 10% until tSTAB has elapsed. See Figure 12: PLL output frequency timing

diagram.

Averaged over a 4ms period. After the LOCKED bit is set, a period of tSTAB is required to reach ACCPLL accuracy.

Guaranteed by design.

Table 65.

RC oscillator and PLL characteristics (tested for TA = -40 to +85°C) @ VDD = 2.7 to

3.3V (continued)

Symbol

Parameter

Conditions

Min

Typ

Max Unit

0.50

0.60

0.70

0.80

0.90

1.00

2.4

2.6

2.8

3.2

3.4

3.6

3.8

VDD (V)

0.00

0.10

0.20

0.30

0.40

0.50

0.60

0.70

0.80

0.90

1.00

1.10

2.5

3.5

4.5

5.5

Vdd (V)

-45°

0°

25°

90°

105°

130°

-1

-5

-45

025

-2

-4

-3

(*)

(*) tested in production

Temperature (°C)

125

ST7LITE20F2 数据表(PDF) 124 Page - STMicroelectronics

ST7LITE20F2 数据表(HTML) 124 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载