ST7LITE20F2 datasheet(126/166 Pages) STMICROELECTRONICS

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Electrical characteristics

ST7LITE20F2 ST7LITE25F2 ST7LITE29F2

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Doc ID 8349 Rev 5

Note:

TA = -40 to 85°C, unless otherwise specified.

13.4

Supply current characteristics

The following current consumption specified for the ST7 functional operating modes over

temperature range does not take into account the clock source current consumption. To get

the total device consumption, the two current values must be added (except for HALT mode

for which the clock is stopped).

Note:

TA = -40 to +85°C unless otherwise specified, VDD=5.5V.

Table 66.

32MHz PLL

Symbol

Parameter

Min

Typ

Max

Unit

VDD

Voltage (1)

32 MHz is guaranteed within this voltage range.

4.5

5.5

fPLL32

Frequency (1)

−

MHz

fINPUT

Input Frequency

MHz

Table 67.

Supply Current

Symbol

Parameter

Conditions

Typ

Max

Unit

IDD

Supply current in Run mode

External Clock, fCPU = 1MHz

(1)

−

Internal RC, fCPU=1MHz

2.2

−

fCPU=8MHz

(1)

7.5

Supply current in WAIT mode

External Clock, fCPU=1MHz

(2)

0.8

−

Internal RC, fCPU=1MHz

1.8

−

fCPU = 8MHz

(2)

3.7

Supply current in SLOW mode

fCPU = 250kHz

(3)

1.6

2.5

Supply current in SLOW-wait mode

fCPU = 250kHz

(4)

1.6

2.5

Supply current in HALT mode(5)

-40°C

≤TA≤+85°C

μA

TA = +125°C

Supply current in AWUF mode(6)

TA = +25°C

CPU running with memory access, all I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals in

reset state; clock input (CLKIN) driven by external square wave, LVD disabled.

All I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals in reset state; clock input (CLKIN)

driven by external square wave, LVD disabled.

SLOW mode selected with fCPU based on fOSC divided by 32. All I/O pins in input mode with a static value at VDD or VSS

(no load), all peripherals in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.

SLOW-WAIT mode selected with fCPU based on fOSC divided by 32. All I/O pins in input mode with a static value at VDD or

VSS (no load), all peripherals in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.

All I/O pins in output mode with a static value at VSS (no load), LVD disabled. Data based on characterization results,

tested in production at VDD max and fCPU max.

All I/O pins in input mode with a static value at VDD or VSS (no load). Data tested in production at VDD max. and fCPU

max.

This consumption refers to the Halt period only and not the associated run period which is software dependent.

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