AM79C978VCSLASHW datasheet(165/261 Pages) AMD

165 / 261 page

Am79C978

165

boundary where the receive buffer

begins in the SRAM. The transmit

buffer in the SRAM begins at ad-

dress 0 and ends at the address

located just before the address

specified by SRAM_BND. There-

fore, the receive buffer always be-

gins on a 512 byte boundary. The

lower bits are assumed to be ze-

ros. SRAM_BND has no effect in

the Low Latency Receive mode.

Note:

The

minimum

allowed

number of pages is four. The

Am79C978 controller will not op-

erate correctly with less than four

pages of memory per queue. See

Table 41 for SRAM_BND pro-

gramming details.

CAUTION:

Programming

SRAM_BND and SRAM_SIZE

to the same value will cause

data corruption except in the

case where SRAM SIZE is 0.

Read accessible always; write

accessible only when the STOP

bit is set. SRAM_BND is set to

00000000b

during

H_RESET

and is unaffected by S_RESET or

STOP.

BCR27: SRAM Interface Control Register

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

PTR TST

Reserved. Reserved for manu-

facturing tests. Written as zero

and read as undefined.

Note: Use of this bit will cause

data corruption and erroneous

operation.

This bit is always read/write ac-

cessible. PTR_TST is set to 0 by

H_RESET and is unaffected by

S_RESET and the STOP bit.

LOLATRX

Low Latency Receive. When the

LOLATRX bit is set to 1, the

Am79C978 controller will switch

to an architecture applicable to

cut-through

switches.

The

Am79C978 controller will assert a

receive frame DMA after only 16

bytes of the current receive frame

has been received regardless of

where the RCVFW (CSR80, bits

13-12) are set. The watermark is

a fixed value and cannot be

changed. The receive FIFOs will

be in NO_SRAM mode while all

transmit traffic is buffered through

the SRAM. This bit is only valid

and the low latency receive only

enabled when the SRAM_SIZE

(BCR25, bits 7-0) bits are non-ze-

ro. SRAM_BND (BCR26, bits 7-

0) has no meaning when the

Am79C978 controller is in the

Low Latency mode. See the sec-

tion on SRAM Configuration for

more details.

When the LOLATRX bit is set to

0, the Am79C978 controller will

return to a normal receive config-

uration. The runt packet accept

bit (RPA, CSR124, bit 3) must be

set when LOLATRX is set.

CAUTION: To provide data in-

tegrity when switching into

and out of the low latency

mode,

NOT

SET

the

FASTSPNDE (CSR7, bit 15) bit

when setting the SPND bit. Re-

ceive frames WILL be overwrit-

ten

and

the

Am79C978

controller may give erratic be-

havior when it is enable again.

The minimum allowed number

pages

four.

The

Am79C978 controller will not

operate correctly in the LOLA-

TRX mode with less than four

pages of memory.

Read/Write accessible only when

the STOP bit is set. LOLATRX is

cleared to 0 after H_RESET or

S_RESET and is unaffected by

STOP.

13-6

RES

Reserved locations. Written as

zeros and read as undefined.

Table 41.

SRAM_BND Programming

SRAM Addresses

SRAM_BND [7:0]

Minimum SRAM_BND

Address

04h

Maximum SRAM_BND Address

13h

AM79C978VC/W 数据表(PDF) 165 Page - Advanced Micro Devices

AM79C978VC/W 数据表(HTML) 165 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载