AM79C978VCSLASHW datasheet(169/261 Pages) AMD

169 / 261 page

Am79C978

169

MII port. When the Auto Select bit

(ASEL, BCR2, bit 1) is a 1 and the

MIIPD bit is a 1, the MII port is se-

lected. Any transition on the MI-

IPD bit will set the MIIPDTI bit in

CSR7, bit 3.

Read accessible always. MIIPD

is read only. Write operations are

ignored and should not be per-

formed.

13-12 FMDC

Fast Management Data Clock (is

used for manufacturing tests).

When FMDC is set to 1h, the MII

Management Data Clock will run

at 5 MHz max. The Management

Data Clock will no longer be IEEE

802.3u-compliant and setting this

bit should be used with care. The

accompanying

external

PHY

must also be able to accept man-

agement frames at the new clock

rate. When FMDC is set to 0h, the

MII Management Data Clock will

run at 2.5 MHz max and will be

fully compliant to IEEE 802.3u

standards. See Table 44.

This bit is always read/write ac-

cessible. FMDC is set to 0 during

H_RESET, and is unaffected by

S_RESET and the STOP bit

APEP

Auto-Poll PHY. When APEP is

set to 1 the Am79C978 controller

will poll the status register in the

PHY. This feature allows the soft-

ware driver or upper layers to see

any changes in the status of the

PHY. An interrupt when enabled

is generated when the contents of

the new status is different from

the previous status.

This bit is always read/write ac-

cessible. APEP is set to 0 during

H_RESET and is unaffected by

S_RESET and the STOP bit.

10-8

APDW

Auto-Poll Dwell Time. APDW de-

termines the dwell time between

PHY

Management

Frame

accesses

when

Auto-Poll

turned on. See Table 45.

This bit is always read/write ac-

cessible. APDW is set to 100h af-

ter H_RESET and is unaffected

by S_RESET and the STOP bit.

DANAS

Disable

Auto-Negotiation

Auto

Setup. When DANAS is set, the

Am79C978

controller

after

H_RESET or S_RESET will re-

main dormant and not automati-

cally startup the Auto-Negotiation

section or the enhanced automat-

ic port selection section. Instead,

the Am79C978 controller will wait

for the software driver to setup

the Auto-Negotiation portions of

the device. The PHY Address

and Data programming in BCR33

and BCR34 is still valid. The

Am79C978

controller

will

not

generate

any

management

frames unless Auto-Poll is en-

abled.

This bit is always read/write ac-

cessible. DANAS is set to 0 by

H_RESET and is unaffected by

S_RESET and the STOP bit.

XPHYRST

PHY Reset. When XPHYRST is

set, the Am79C978 controller af-

ter an H_RESET or S_RESET

will issue management frames

that will reset the PHY. This bit is

needed when there is no way to

guarantee the state of the exter-

nal PHY. This bit must be repro-

grammed after every H_RESET.

Table 44.

FMDC Values

FMDC

Fast Management Data Clock

2.5 MHz max

5 MHz max

Reserved

Table 45.

APDW Values

APDW

Auto-Poll

 Dwell Time

000

Continuous (26

µs @ 2.5 MHz)

001

Every 128 MDC cycles (103

µs @ 2.5 MHz)

010

Every 256 MDC cycles (206

µs @ 2.5 MHz)

011

Every 512 MDC cycles (410

µs @ 2.5 MHz)

100

Every 1024 MDC cycles (819

µs @ 2.5 MHz)

101

Every 2048 MDC cycles (1640

µs @ 2.5 MHz)

110-111 Reserved

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