AM79C978VCSLASHW datasheet(170/261 Pages) AMD

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170

Am79C978

This bit is always read/write ac-

cessible. XPHYRST is set to 0 by

H_RESET and is unaffected by

S_RESET and the STOP bit.

XPHYRST is only valid when the

internal Network Port Manager is

scanning for a network port.

XPHYANE

PHY Auto-Negotiation Enable.

This bit will force the PHY into en-

abling Auto-Negotiation. When

set to 0 the Am79C978 controller

will send a management frame

disabling Auto-Negotiation.

This bit is always read/write ac-

cessible. XPHYANE is set to 0 by

H_RESET and is unaffected by

S_RESET and the STOP bit.

XPHYANE is only valid when the

internal Network Port Manager is

scanning for a network port.

XPHYFD

PHY Full Duplex. When set, this

bit will force the PHY into full du-

plex when Auto-Negotiation is not

enabled.

This bit is always read/write ac-

cessible. XPHYFD is set to 0 by

H_RESET, and is unaffected by

S_RESET and the STOP bit.

XPHYSP

PHY Speed. When set, this bit

will force the PHY into 100 Mbps

mode when Auto-Negotiation is

not enabled.

This bit is always read/write ac-

cessible. XPHYSP is set to 0 by

H_RESET, and is unaffected by

S_RESET and the STOP bit.

RES

Reserved location. Written as

zero and read as undefined.

MIIILP

Media Independent Interface In-

ternal Loopback. When set, this

bit will cause the internal portion

of the MII data port to loopback

on itself. The interface is mapped

the

following

way.

The

TXD[3:0] nibble data path is

looped back onto the RXD[3:0]

nibble data path. TX_CLK is

looped back as RX_CLK. TX_EN

is looped back as RX_DV. CRS is

correctly OR’d with TX_EN and

RX_DV and always encompass-

es the transmit frame. TX_ER is

looped back as RX_ER. Howev-

er, TX_ER will not get asserted

by the Am79C978 controller to

signal an error. The TX_ER func-

tion is reserved for future use.

This bit is always read/write ac-

cessible. MIIILP is set to 0 by

H_RESET and is unaffected by

S_RESET and the STOP bit.

RES

Reserved location. Written as

zero and read as undefined.

BCR33: PHY Address Register

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

SHADOW

If the user wishes to update the

contents of the BCR33 shadow

value written into BCR33 (bit 15)

will enable the contents to be si-

multaneously written to BCR33

shadow.

MII_SEL

MII selected. This bit indicates

whether the internal PHY is se-

lected.

AUTONEG_COMPLETE

Internal Auto-Negotiation com-

plete. Valid for internal PHY only.

LINK STATUS

Link Status. This bit is a valid link

status indication.

FULL_DUPLEX

Full Duplex. This bit indicates that

the MAC is configured for Full-

Duplex operation.

SPEED_SEL Speed Selected. This bit indi-

cates if High or Low speed has

been selected by MAC.

9-5

PHYAD

Management Frame PHY Ad-

dress. PHYAD contains the 5-bit

PHY Address field that is used in

the management frame that gets

clocked out via the MII manage-

ment port pins (MDC and MDIO)

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AM79C978VC/W 数据表(PDF) 170 Page - Advanced Micro Devices

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