AM79C978VCSLASHW datasheet(166/261 Pages) AMD

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166

Am79C978

5-3

EBCS

Expansion Bus Clock Source.

These bits are used to select the

source of the fundamental clock

to drive the SRAM and Expansion

ROM access cycles. Table 42

shows the selected clock source

for the various values of EBCS.

Note that the actual frequency

that the Expansion Bus access

cycles run at is a function of both

the

EBCS

and

CLK_FAC

(BCR27, bits 2-0) bit field set-

tings. When EBCS is set to either

the PCI clock or the Time Base

clock, no external clock source is

required as the clocks are routed

internally and the EBCLK pin

should be pulled to VDD through

a resistor.

Read accessible always; write

accessible only when the STOP

bit is set. EBCS is set to 000b

(PCI

clock

selected)

during

H_RESET and is unaffected by

S_RESET or the STOP bit.

Note: The clock frequency driv-

ing the Expansion Bus access cy-

cles that results from the settings

of the EBCS and CLK FAC bits

must not exceed 33 MHz at any

time. When EBCS is set to either

the PCI clock or the Time Base

clock, no external clock source is

required because the clocks are

routed internally and the EBCLK

pin should be pulled to VDD

through a resistor.

CAUTION: Care should be ex-

ercised when choosing the PCI

clock pin because of the nature

of the PCI clock signal. The PCI

specification states that the

PCI clock can be stopped. If

that can occur while it is being

used for the Expansion Bus

clock data, corruption will re-

sult.

CAUTION:

The

Time

Base

Clock will not support 100

Mbps operation and should

only be selected in 10 Mbps-

only configurations.

CAUTION: The external clock

source

used

drive

the

EBCLK pin must be a continu-

ous clock source at all times.

2-0

CLK_FAC

Clock Factor. These bits are used

to select whether the clock select-

ed by EBCS is used directly or if it

is divided down to give a slower

clock for running the Expansion

Bus access cycles. The possible

factors are given in Table 43.

Read accessible always; write

accessible only when the STOP

bit is set. CLK_FAC is set to 000b

during H_RESET and is unaffect-

ed by S_RESET or STOP.

BCR28: Expansion Bus Port Address Lower (Used

for Flash/EPROM and SRAM Accesses)

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

15-0

EPADDRL

Expansion Port Address Lower.

This address is used to provide

addresses for the Flash and

SRAM port accesses.

SRAM

accesses

are

started

when a read or write is performed

on BCR30 and the FLASH (BCR

29, bit 15) is set to 0. During

SRAM accesses only bits in the

EPADDRL are valid. Since all

SRAM accesses are word orient-

ed only, EPADDRL[0] is the least

significant word address bit. On

Table 42.

EBCS Values

EBCS

Expansion Bus Clock Source

000

CLK pin (PCI Clock)

001

Time Base Clock

010

EBCLK pin

011

Reserved

1XX

Reserved

Table 43.

CLK_FAC Values

CLK_FAC

Clock Factor

000

001

1/2 (divide by 2)

010

Reserved

011

1/4 (divide by 4)

1XX

Reserved

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