AM79C978VCSLASHW datasheet(161/261 Pages) AMD

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Am79C978

161

Table 38.

EEDET Setting

ESK

EEPROM Serial Clock. This bit

and the EDI/EDO bit are used to

control host access to the EE-

PROM. Values programmed to

this bit are placed onto the EESK

pin at the rising edge of the next

clock following bit programming,

except when the PREAD bit is set

to 1 or the EEN bit is set to 0. If

both the ESK bit and the EDI/

EDO bit values are changed dur-

ing one BCR19 write operation,

while EEN = 1, then setup and

hold times of the EEDI pin value

with respect to the EESK signal

edge are not guaranteed.

ESK has no effect on the EESK

pin unless the PREAD bit is set to

0 and the EEN bit is set to 1.

This bit is read accessible al-

ways, write accessible only when

either the STOP or the SPND bit

is set. ESK is reset to 1 by

H_RESET and is not affected by

S_RESET or STOP.

EDI/EDO

EEPROM

Data

In/EEPROM

Data Out. Data that is written to

this bit will appear on the EEDI

output of the interface, except

when the PREAD bit is set to 1 or

the EEN bit is set to 0. Data that

is read from this bit reflects the

value of the EEDO input of the in-

terface.

EDI/EDO has no effect on the

EEDI pin unless the PREAD bit is

set to 0 and the EEN bit is set to

Read accessible always; write

accessible only when either the

STOP or the SPND bit is set. EDI/

EDO is reset to 0 by H_RESET

and is not affected by S_RESET

or STOP.

BCR20: Software Style

This register is an alias of the location CSR58. Accesses

to and from this register are equivalent to accesses to

CSR58.

Bit

Name

Description

31-11 RES

Reserved locations. Written as

zeros and read as undefined.

EEDET Value

(BCR19[13])

EEPROM

Connected?

Result if PREAD is Set to 1

Result of Automatic EEPROM Read

Operation Following H_RESET

EEPROM read operation is attempted.

Entire read sequence will occur, checksum

failure will result, PVALID is reset to 0.

First two EESK clock cycles are generated,

then EEPROM read operation is aborted

and PVALID is reset to 0.

Yes

EEPROM read operation is attempted.

Entire read sequence will occur, checksum

operation will pass, PVALID is set to 1.

First two EESK clock cycles are generated,

then EEPROM read operation is aborted

and PVALID is reset to 0.

EEPROM read operation is attempted.

Entire read sequence will occur, checksum

failure will result, PVALID is reset to 0.

EEPROM read operation is attempted.

Entire read sequence will occur, checksum

failure will result, PVALID is reset to 0.

Yes

EEPROM read operation is attempted.

Entire read sequence will occur, checksum

operation will pass, PVALID is set to 1.

EEPROM read operation is attempted.

Entire read sequence will occur, checksum

operation will pass, PVALID is set to 1.

Table 39.

Interface Pin Assignment

RST Pin

PREAD or Auto

Read in Progress

EEN

EECS

EESK

EEDI

Low

Tri-State

High

Active

High

From ECS

Bit of BCR19

From ESK Bit of

BCR19

From EEDI Bit of

BCR19

High

LED1

LED0

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