AM79C978VCSLASHW datasheet(157/261 Pages) AMD

157 / 261 page

Am79C978

157

Setting the NOUFLO bit guaran-

tees that the Am79C978 control-

ler will never suffer transmit

underflows, because the arbiter

that controls transfers to and from

the SRAM guarantees a worst

case latency on transfers to and

from the MAC and Bus Transmit

FIFOs such that it will never un-

derflow if the complete packet

has

been

DMA’d

into

the

Am79C978

controller

before

packet transmission begins.

The NOUFLO bit has no effect

when the Am79C978 controller is

operating in the NO-SRAM mode.

Read/Write accessible only when

either the STOP or the SPND bit

is set. NOUFLO is cleared to 0 af-

ter H_RESET or S_RESET and

is unaffected by STOP.

RES

Reserved location. Written as

zero and read as undefined.

MEMCMD

Memory Command used for burst

read accesses to the transmit

buffer. When MEMCMD is set to

0, all burst read accesses to the

transmit buffer are of the PCI

command type Memory Read

Line (type 14). When MEMCMD

is set to 1, all burst read accesses

to the transmit buffer are of the

PCI

command

type

Memory

Read Multiple (type 12).

This bit is read accessible al-

ways; write accessible only when

either the STOP or the SPND bit

is set. MEMCMD is cleared by

H_RESET and is not affected by

S_RESET or STOP.

EXTREQ

Extended Request. This bit con-

trols the deassertion of REQ for a

burst transaction. If EXTREQ is

set to 0, REQ is deasserted at the

beginning of a burst transaction.

(The Am79C978 controller never

performs more than one burst

transaction within a single bus

mastership period.) In this mode,

the Am79C978 controller relies

on the PCI latency timer to get

enough bus bandwidth, in case

the system arbiter also removes

GNT at the beginning of the burst

transaction. If EXTREQ is set to

1, REQ stays asserted until the

last but one data phase of the

burst transaction is done. This

mode is useful for systems that

implement an arbitration scheme

without preemption and require

that REQ stays asserted through-

out the transaction.

EXTREQ should not be set to 1

when the Am79C978 controller is

used in a PCI bus application.

This bit is read accessible al-

ways, write accessible only when

either the STOP or the SPND bit

is set. EXTREQ is cleared by

H_RESET and is not affected by

S_RESET or STOP.

DWIO

Double Word I/O. When set, this

bit indicates that the Am79C978

controller

programmed

for

DWord I/O (DWIO) mode. When

cleared, this bit indicates that the

Am79C978

controller

pro-

grammed for Word I/O (WIO)

mode. This bit affects the I/O Re-

source Offset map and it affects

the

defined

width

the

Am79C978 controller’s I/O re-

sources. See the DWIO and WIO

sections for more details.

The initial value of the DWIO bit is

determined by the programming

of the EEPROM.

The value of DWIO can be al-

tered

automatically

the

Am79C978 controller. Specifical-

ly, the Am79C978 controller will

set DWIO if it detects a DWord

write access to offset 10h from

the Am79C978 controller’s I/O

base address (corresponding to

the RDP resource).

Once the DWIO bit has been set

to a 1, only a H_RESET or an EE-

PROM read can reset it to a 0.

(Note that the EEPROM read op-

eration will only set DWIO to a 0 if

the appropriate bit inside of the

EEPROM is set to 0.)

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