AM79C978VCSLASHW datasheet(155/261 Pages) AMD

155 / 261 page

Am79C978

155

tivity on the network.

This bit is always read/write ac-

cessible. RCVE is cleared by

H_RESET and is not affected by

S_RESET or setting the STOP

bit.

SPEED

Speed. When this bit is set to 1,

the device is operating in HIGH

speed mode.

COLE

Collision Status Enable. When

this bit is set, a value of 1 is

passed to the LEDOUT bit in this

activity on the network.

This bit is always read/write ac-

cessible. COLE is cleared by

H_RESET and is not affected by

S_RESET or setting the STOP

bit.

BCR9: Full-Duplex Control

Note: Bits 15-0 in this register are programmable

through the EEPROM.

Bit

Name

Description

31-3

RES

Reserved locations. Written as

zeros and read as undefined.

FDRPAD

Full-Duplex Runt Packet Accept

Disable. When FDRPAD is set to

1 and full-duplex mode is en-

abled, the Am79C978 controller

will only receive frames that meet

the

minimum

Ethernet

frame

length of 64 bytes. Receive DMA

will not start until at least 64 bytes

or a complete frame have been

received. By default, FDRPAD is

cleared to 0. The Am79C978 con-

troller will accept any length

frame and receive DMA will start

according to the programming of

the

receive

FIFO

watermark.

Note that there should not be any

runt packets in a full-duplex net-

work, since the main cause for

runt packets is a network collision

and there are no collisions in a

full-duplex network.

This bit is always read/write ac-

cessible. FDRPAD is cleared by

H_RESET and is not affected by

S_RESET or by setting the STOP

bit.

RES

Reserved locations. Written as

zeros and read as undefined.

FDEN

Full-Duplex Enable. FDEN con-

trols whether full-duplex opera-

tion is enabled. When FDEN is

cleared and the Auto-Negotiation

is disabled, full-duplex operation

not

enabled

and

the

Am79C978 controller will always

operate

half-duplex

mode.

When

FDEN

set,

the

Am79C978 controller will operate

in full-duplex mode. Do not set

this bit when Auto-Negotiation

is enabled.

This bit is always read/write ac-

cessible. FDEN is reset to 0 by

H_RESET, and is unaffected by

S_RESET and the STOP bit.

BCR16: I/O Base Address Lower

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

15-5

IOBASEL

Reserved

locations.

After

H_RESET, the value of these bits

will be undefined. The settings of

these bits will have no effect on

any Am79C978 controller func-

tion.

These bits are always read/write

accessible. IOBASEL is not af-

fected by S_RESET or STOP.

4-0

RES

Reserved locations. Written as

zeros, read as undefined.

BCR17: I/O Base Address Upper

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

15-0

IOBASEU

Reserved

locations.

After

H_RESET, the value in this regis-

ter will be undefined. The settings

of this register will have no effect

any

Am79C978

controller

function.

AM79C978VC/W 数据表(PDF) 155 Page - Advanced Micro Devices

AM79C978VC/W 数据表(HTML) 155 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

AM79C978VC/W 数据表(PDF) 155 Page - Advanced Micro Devices

AM79C978VC/W 数据表(HTML) 155 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载