AM79C978VCSLASHW datasheet(158/261 Pages) AMD

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158

Am79C978

This bit is read accessible al-

ways. DWIO is read only, write

operations have no effect. DWIO

is cleared by H_RESET and is

not affected S_RESET or by set-

ting the STOP bit.

BREADE

Burst Read Enable. When set,

this bit enables burst mode during

memory read accesses. When

cleared, this bit prevents the de-

vice from performing bursting

during

read

accesses.

The

Am79C978 controller can per-

form burst transfers when reading

the initialization block, the de-

scriptor

ring

entries

(when

SWSTYLE = 3), and the buffer

memory.

BREADE should be set to 1 when

the Am79C978 controller is used

in a PCI bus application to guar-

antee maximum performance.

This bit is read accessible al-

ways; write accessible only when

either the STOP or the SPND bit

is set. BREADE is cleared by

H_RESET and is not affected by

S_RESET or STOP.

BWRITE

Burst Write Enable. When set,

this bit enables burst mode during

memory write accesses. When

cleared, this bit prevents the de-

vice from performing bursting

during

write

accesses.

The

Am79C978 controller can per-

form burst transfers when writing

the descriptor ring entries (when

SWSTYLE = 3), and the buffer

memory.

BWRITE should be set to 1 when

the Am79C978 controller is used

in a PCI bus application to guar-

antee maximum performance.

This bit is read accessible al-

ways, write accessible only when

either the STOP or the SPND bit

is set. BWRITE is cleared by

H_RESET and is not affected by

S_RESET or STOP.

4-3

PHYSEL[1:0] PHYSEL[1:0] bits allow for soft-

ware controlled selection of differ-

ent operation and test modes.

The normal mode of operation is

when both bits 0 and 1 are set to

0 to select the Expansion ROM/

Flash. Setting bit 0 to 1 and bit 1

to 0 allows snooping of the inter-

nal MII-compatible bus to allow

External Address Detection Inter-

face (EADI). See Table 37 for de-

tails.

Table 37.

PHY Select Programming

These bits are read accessible al-

ways, these bits can only be writ-

ten from the EEPROM unless a

write-enable bit, BCR2[13], is set.

PHYSEL

[1:0]

cleared

H_RESET and is not affected by

S_RESET or STOP.

2-0

LINBC

Reserved locations. These bits

are read accessible always; write

accessible only when either the

STOP or the SPND bit is set. Af-

ter H_RESET, the value in these

bits will be 001b. The setting of

these bits have no effect on any

Am79C978 controller’s function.

LINBC

not

affected

S_RESET or STOP.

BCR19: EEPROM Control and Status

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

PVALID

EEPROM Valid status bit. This bit

is read accessible only. PVALID

is read only; write operations

have no effect. A value of 1 in this

bit indicates that a PREAD opera-

tion has occurred, and that (1)

there is an EEPROM connected

to the Am79C978 controller inter-

face pins and (2) the contents

read from the EEPROM have

passed the checksum verification

operation.

PHYSEL [1:0]

Mode

Expansion ROM/Flash

EADI/Internal MII Snoop

Reserved

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