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SPEAR320S 数据表(PDF) 52 Page - STMicroelectronics |
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SPEAR320S 数据表(HTML) 52 Page - STMicroelectronics |
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52 / 113 page  Pin description SPEAr320S 52/113 Doc ID 022508 Rev 2 Table 19. CLCD signals description Signal name Description Dir. PL_GPIO_# /Ball Configuration mode CLAC STN AC bias drive or TFT data enable output O PL_GPIO_73/A17 1, Extended CLCP LCD panel clock O PL_CLK1/K17 1, Extended CLD0 LCD panel data O PL_GPIO_97/H16 1, Extended CLD1 PL_GPIO_96/H15 CLD2 PL_GPIO_95/H14 CLD3 PL_GPIO_94/H13 CLD4 PL_GPIO_93/G17 CLD5 PL_GPIO_92/G16 CLD6 PL_GPIO_91/G15 CLD7 PL_GPIO_90/G14 CLD8 PL_GPIO_89/F17 CLD9 PL_GPIO_88/F16 CLD10 PL_GPIO_87/G13 CLD11 PL_GPIO_86/E17 CLD12 PL_GPIO_85/F15 CLD13 PL_GPIO_84/D17 CLD14 PL_GPIO_83/E16 CLD15 PL_GPIO_82/E15 CLD16 PL_GPIO_81/C17 CLD17 PL_GPIO_80/D16 CLD18 PL_GPIO_79/F14 CLD19 PL_GPIO_78/D15 CLD20 PL_GPIO_77/B17 CLD21 PL_GPIO_76/F13 CLD22 PL_GPIO_75/E14 CLD23 PL_GPIO_74/C16 CLFP Frame pulse (STN)/ vertical synchronization pulse (TFT) O PL_GPIO_72/B16 1, Extended CLLE Line end signal O PL_GPIO_70/C15 1, Extended CLLP Line synchronization pulse (STN)/ horizontal synchronization pulse (TFT) O PL_GPIO_71/D14 1, Extended CLPOWER LCD panel power enable O PL_GPIO_69/A16 1, Extended |
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