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SPEAR320S 数据表(PDF) 98 Page - STMicroelectronics |
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SPEAR320S 数据表(HTML) 98 Page - STMicroelectronics |
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98 / 113 page  Timing requirements SPEAr320S 98/113 Doc ID 022508 Rev 2 5.16 SSP timing characteristics This section describes the timing characteristics of the synchronous serial port. Note: Note:The characterization of the SSP has been done using the SPI protocol. Figure 31. SSP_SCK waveform The clock polarity parameter (SPO) indicates the state of the clock signal when it is idle. This can be programmed in the SSPCR0 register. SPO= 0 The clock idle state is low. SPO= 1 The clock idle state is high. 5.16.1 SPI master mode timings SSP_SCK is the SPI output clock. TPCLK is the clock period of the PCLK internal clock. Figure 32. SPI master mode external timing waveform (SPH= 0, SPO =0 ) TCLKhigh T CLKlow TCLK SSP_SCK (SPO=0) SSP_SCK (SPO=1) DATA MSB IN LSB IN LSB OUT DATA MSB OUT SSP_SS#n SSP_SCK (SPO=0) SSP_MISO (input) SSP_MOSI (output) T SU T H T D2 T D1 T D3 |
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