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SPEAR320S 数据表(PDF) 83 Page - STMicroelectronics |
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SPEAR320S 数据表(HTML) 83 Page - STMicroelectronics |
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83 / 113 page  SPEAr320S Timing requirements Doc ID 022508 Rev 2 83/113 5.6 EMI timing characteristics Figure 13. EMI read cycle waveform with acknowledgement on EMI_WAIT Note: The values of tSE, tENr, tDCS, tSCS are programmable via the EMI registers. Note: Values in Table 56 refer to the common internal source clock which has a period of tHCLK = 6 ns. Figure 14. EMI write cycle waveform with acknowledgement on EMI_WAIT Note: The values of tSE, tENw, tDCS, tSCS are programmable via the EMI registers. EMI_A# EMI_BYTEN# EMI_D# EMI_CEn# EMI_OE Address Byte Enable Data tSE tSCS tENr tDCS EMI_WAIT tCS->Wait tWAIT Table 56. EMI timing requirements for read cycle with acknowledgement on WAIT Symbol Min tCS->Wait tHCLK tWAIT 4*tHCLK EMI_A# EMI_BYTEN# EMI_D# EMI_CEn# EMI_WE Write Data Byte Enable Data tSE tSCS tENw tDCS EMI_WAIT tCS->tWAIT tWAIT |
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