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SPEAR320S 数据表(PDF) 41 Page - STMicroelectronics |
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SPEAR320S 数据表(HTML) 41 Page - STMicroelectronics |
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41 / 113 page  SPEAr320S Pin description Doc ID 022508 Rev 2 41/113 3.4.5 Boot pins The status of the boot pins is read at startup by the BootROM. The H[7:0] pins are user-definable strapping option pins. The values of the pins are latched at startup and are readable from a register. 3.4.6 GPIOs The PL_GPIO pins can be used as software-controlled general purpose I/Os if they are not used by the interfaces of embedded IPs mapped on same pins. Table 14. Boot pins description B3 B2 B1 B0 Boot device 0000 USB Device 0001 Ethernet MII0 (MAC address in I2C non-volatile memory) 0010 Ethernet MII0 (MAC address in SPI non-volatile memory) 0011 Serial NOR Flash (SMI interface) 0100 Parallel 8-bit NOR Flash (EMI interface) 0101 Parallel 16-bit NOR Flash (EMI interface) 0110 Parallel 8-bit NAND Flash (FSMC interface) 0111 Parallel 16-bit NAND Flash (FSMC interface) 1010 UART0 1011 Bypass BootROM and boot from serial NOR Flash (SMI interface) Other Reserved |
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