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SPEAR320S 数据表(PDF) 100 Page - STMicroelectronics |
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SPEAR320S 数据表(HTML) 100 Page - STMicroelectronics |
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100 / 113 page  Timing requirements SPEAr320S 100/113 Doc ID 022508 Rev 2 Figure 33. SPI master mode external timing waveform (SPH= 0, SPO =1 ) DATA MSB IN LSB IN LSB OUT DATA MSB OUT SSP_SS#n SSP_SCK (SPO=1) SSP_MISO (input) SSP_MOSI (output) T SU T D1 T H T D3 T D2 Table 75. SPI master mode timing characteristics (SPH = 0, SPO=1) Symbol Parameters Min Max Unit TSU Setup time, MISO (input) valid before SSP_SCK (output) falling edge SSP0 7.8 ns SSP1 16 SSP2 15.55 TH Hold time, MISO (input) valid after SSP_SCK (output) falling edge SSP0 -2.7 SSP1 -4 SSP2 -4.6 TD1 Delay time, SSP_SS#n (output) falling edge to first SSP_SCK (output) falling edge SSP0 TSSP_SCK-10 TSSP_SCK-3 ns SSP1 TSSP_SCK-6.4 TSSP_SCK-0.9 SSP2 TSSP_SCK-5.87 TSSP_SCK-0.03 TD2 Delay time, SSP_SCK (output) rising edge to MOSI (output) transition SSP0 2.7 9.5 ns SSP1 0.57 5.34 SSP2 0.2 5.53 TD3 Delay time, SSP_SCK (output) rising edge to SSP_SS#n (output) rising edge SSP0 (TSSP_SCK /2)+ 3 (TSSP_SCK/2) +8 SSP1 (TSSP_SCK /2)+ 0.9 (TSSP_SCK/2) +6.4 SSP2 (TSSP_SCK /2)-0.03 (TSSP_SCK/2) +5.87 |
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