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SPEAR320S 数据表(PDF) 101 Page - STMicroelectronics |
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SPEAR320S 数据表(HTML) 101 Page - STMicroelectronics |
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101 / 113 page  SPEAr320S Timing requirements Doc ID 022508 Rev 2 101/113 Figure 34. SPI master mode external timing waveform (SPH = 1, SPO = 0) DATA MSB IN LSB IN LSB OUT DATA MSB OUT SSP_SS#n SSP_SCK (SPO=0) SSP_MISO (input) SSP_MOSI (output) T SU T H T D2 T D3 T D1 Table 76. SPI master mode timing characteristics (SPH = 1, SPO=0) Symbol Parameters Min Max Unit TSU Setup time, MISO (input) valid before SSP_SCK (output) falling edge SSP0 7.8 ns SSP1 16 SSP2 15.55 TH Hold time, MISO (input) valid after SSP_SCK (output) falling edge SSP0 -2.7 SSP1 -4 SSP2 -4.6 TD1 Delay time, SSP_SS#n (output) falling edge to first SSP_SCK (output) falling edge SSP0 (TSSP_SCK/2)-10 (TSSP_SCK/2)-3 ns SSP1 (TSSP_SCK/2)-6.4 (TSSP_SCK/2)-0.9 SSP2 (TSSP_SCK/2)-5.87 (TSSP_SCK/2)-0.03 TD2 Delay time, SSP_SCK (output) rising edge to MOSI (output) transition SSP0 2.7 9.5 ns SSP1 0.57 5.34 SSP2 0.2 5.53 TD3 Delay time, SSP_SCK (output) rising edge to SSP_SS#n (output) rising edge SSP0 TSSP_SCK + 3 (TSSP_SCK +10 SSP1 TSSP_SCK + 0.9 (TSSP_SCK +6.4 SSP2 TSSP_SCK -0.03 TSSP_SCK +5.87 |
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