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SPEAR320S 数据表(PDF) 105 Page - STMicroelectronics |
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SPEAR320S 数据表(HTML) 105 Page - STMicroelectronics |
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105 / 113 page ![]() SPEAr320S Timing requirements Doc ID 022508 Rev 2 105/113 Note: 1 The time value depends upon the CPU frequency to write and read registers. 2 It also depends on the UART clock frequency used to set its flag register bit to indicate the end of transmission. For example: For tD2, the above values are with respect to 83 MHz PCLK and UARTCLK 83 MHz. Table 81. RS485_OE transmit and receive timing characteristics Symbol Parameters Min Max Unit tD1 Delay from OE enable till UART first bit transmission 500 ns tD2 Delay from UART last bit transmission till OE enable 900 ns |
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