SPEAR320S datasheet(27/113 Pages) STMICROELECTRONICS

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SPEAr320S

Device functions

Doc ID 022508 Rev 2

27/113

transient interrupt occurs, the priority logic of the VIC is not set, and lower priority interrupts

can interrupt the transient interrupt service routine, assuming interrupt nesting is permitted.

There are 32 interrupt lines. The VIC uses a bit position for each different interrupt source.

The software can control each request line to generate software interrupts. There are 16

vectored interrupts. These interrupts can only generate an IRQ interrupt. The vectored and

non-vectored IRQ interrupts provide an address for an interrupt service routine (ISR). The

FIQ interrupt has the highest priority, followed by interrupt vector 0 to interrupt vector 15.

Non-vectored IRQ interrupts have the lowest priority.

The specific interrupt map for the SPEAr320S device is documented in the companion

reference manuals.

2.27

Watchdog timer (WDT)

The ARM watchdog module consists of a 32-bit down counter with a programmable time-out

interval that has the capability to generate an interrupt and a reset signal on timing out. The

watchdog module is intended to be used to apply a reset to a system in the event of a

software failure.

2.28

Real-time clock (RTC)

The real-time clock provides an 1-second resolution clock. This keeps time when the system

is inactive and can be used to wake the system up when a programmed alarm time is

reached.

Main features:

●

Time-of-day clock in 24 hour mode

●

Calendar

●

Alarm capability

●

Isolation mode, allowing RTC to work even if power is not supplied to the rest of the

device.

2.29

DMA controller (DMAC)

SPEAr320S provides one DMA controller.

Main features:

●

Able to service up to 8 independent DMA channels for serial data transfers between

single source and destination (for instance, memory-to-memory, memory-to-peripheral,

peripheral to- memory, and peripheral-to-peripheral).

●

Each DMA channel can support a unidirectional transfer, with internal four-word FIFO

per channel.

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