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SPEAR320S 数据表(PDF) 11 Page - STMicroelectronics

部件名 SPEAR320S
功能描述  Embedded MPU with ARM926 core for industrial and consumer applications
PDF  113 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

SPEAR320S 数据表(HTML) 11 Page - STMicroelectronics

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SPEAr320S
Device functions
Doc ID 022508 Rev 2
11/113
2
Device functions
2.1
CPU subsystem
The core of the SPEAr320S is an ARM926EJ-S reduced instruction set computer (RISC)
processor.
Main features:
Supports the 32-bit ARM and 16-bit Thumb instruction sets, enabling the user to trade
off between high performance and high code density. It also includes features for
efficient execution of Java byte codes.
The ARM CPU can be clocked at a frequency up to 333 MHz and includes both an
instruction (16 KB) and a data cache (16 KB). In addition to the capability of running
any real-time operating system (RTOS) available for ARM9 processors, the
ARM926EJ-S subsystem also provides a memory management unit (MMU) that
enables to support high-level operating systems (HLOS) like Linux and Windows
Embedded Compact 7.
Includes an embedded trace module (ETM Medium+) for real-time CPU activity tracing
and debugging. It supports 4-bit and 8-bit normal trace mode and 4-bit demultiplexed
trace mode, with normal or half-rate clock.
For detailed information, please refer to the following public documents available from the
ARM Ltd. website:
CPU Core:
ARM9EJ-S, Technical Reference Manual, Revision: r1p2
http://infocenter.arm.com/help/topic/com.arm.doc.ddi0222b/DDI0222.pdf
CPU Subsystem:
ARM926EJ-S, Technical Reference Manual, Revision: r0p5
http://infocenter.arm.com/help/topic/com.arm.doc.ddi0198e/DDI0198E_arm926ejs_r0p
5_trm.pdf
2.2
Internal memories (BootROM/SRAM)
SPEAr320S integrates two embedded memories:
32 KB ROM (BootROM), storing a factory-defined device bootstrap firmware.
8 KB Static RAM (SRAM), partly used by bootstrap firmware, but also available as
general-purpose memory after system startup.
The firmware in BootROM is automatically executed after SPEAr320S reset and supports
the following bootstrap modes:
Boot from serial NOR Flash
Boot from parallel NAND Flash
Boot from parallel NOR Flash
Boot from USB Device port
Boot from UART0
Boot from Ethernet (MII0)



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