SPEAR320S datasheet(66/113 Pages) STMICROELECTRONICS

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Pin description

SPEAr320S

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Doc ID 022508 Rev 2

3.5

PL_GPIO and PL_CLK pin sharing for debug and test modes

In some cases the PL_GPIO and PL_CLK pins may be used in different ways for debugging

purposes. There are four different cases (see also Table 32):

Case 0 - All the PL_GPIO and PL_CLK get values from Boundary scan registers during

Ex-test instruction of JTAG . Typically, this configuration is used to verify the

correctness of the soldering process during the production flow. The pad (PL_GPIO or

PL_CLK) is driven by the Boundary Scan Register, and disconnected from the I/O

function used in functional mode.

Case 1 - All the PL_GPIO and PL_CLK maintain their original meaning and the JTAG

Interface is disconnected from the processor.

Case 2 - All the PL_GPIO and PL_CLKmaintain their original meaning but the JTAG

Interface is connected to the processor. This configuration is useful during the

development phase, but offers only “static” debug.

Case 3 - Some PL_GPIOs, as shown in Table 32 below, are used to connect the ETM9

lines to an external box. This configuration is typically used only during the

development phase. It offers a very powerful debug capability. When the processor

reaches a breakpoint it is possible, by analyzing the trace buffer, to understand the

reason why the processor has reached the break.

Table 32.

Ball sharing during debug

Signals

Case 0 - boundary

scan

Case 1 - no debug

Case 2 - static debug

Case 3 - full debug

TEST_0

TEST_1

TEST_2

TEST_3

TEST_4

nTRST

nTRST_bscan

nTRST_ARM

TCK

TCK_bscan

TCK_ARM

TMS

TSM_bscan

TMS_ARM

TDI

TDI_bscan

TDI_ARM

TDO

TDO_bscan

TDO_ARM

PL_GPIOxxx/

PL_CLKx

(all pins)

Used for boundary

scan

Functional mode

PL_GPIO97-

PL_GPIO73 used for

debug, Refer to

Table 15:

PL_GPIO/PL_CLK

multiplexing scheme

and reset states on

page 43

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