SPEAR320S datasheet(63/113 Pages) STMICROELECTRONICS

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SPEAr320S

Pin description

Doc ID 022508 Rev 2

63/113

MII0_TXCLK

Transmission clock

This is the transmission clock (25/2.5

MHz in 100 M/10 Mbps) provided by the

external PHY for the MII interface. All the

MII0_TXDn signals generated by the

MAC are synchronous to this clock.

PL_GPIO_27/B6

Alternate function

MII0_TXD0

PHY transmit data.

These bits provide the MII transmit data

nibble. The validity of the data is qualified

with MII0_TXEN and MII0_TXER.

PL_GPIO_26/A5

Alternate function

MII0_TXD1

PL_GPIO_25/C6

Alternate function

MII0_TXD2

PL_GPIO_24/B5

Alternate function

MII0_TXD3

PL_GPIO_23/A4

Alternate function

MII0_TXEN

PHY transmit data enable

When high, it indicates that valid data is

being transmitted on the MII0_TXDn bus.

PL_GPIO_22/D6

Alternate function

MII0_TXER

PHY transmit error

When high, indicates a transmit error or

carrier extension on the MII0_TXDn bus.

PL_GPIO_21/C5

Alternate function

MII1

MII1_COL

PHY collision

This signal is asserted by the PHY when

a collision is detected on the medium.

This signal is not synchronous to any

clock. (Active high)

PL_GPIO_83/E16

2, Extended

MII1_CRS

PHY CRS

This signal is asserted by the PHY when

either the transmit or receive medium is

not idle. The PHY deasserts this signal

when both transmit and receive medium

are idle. This signal is not synchronous to

any clock. (Active high)

PL_GPIO_82/E15

2, Extended

MII1_MDC

Management data clock

The MAC provides timing reference for

the MII1_MDIO signal through this

aperiodic clock. The maximum frequency

of this clock is 2.5 MHz.This clock is

generated inside the Ethernet controller

from the application clock (HCLK) via a

clock divider.

PL_GPIO_80/D16

2, Extended

MII1_MDIO

Management data input/output

PL_GPIO_81/C17

2, Extended

MII1_RXCLK

This is the reception clock (25/2.5 MHz in

100M/10Mbps) provided by the external

PHY for MII interfaces. All MII1_RXDn

signals that the Ethernet controller

receives are synchronous to this clock.

PL_GPIO_90/G14

2, Extended

Table 31.

Ethernet signals description (continued)

Signal name

Description

Dir.

PL_GPIO_# /

ball number

Configuration mode

(see Section 3.4.2)

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