SPEAR320S datasheet(25/113 Pages) STMICROELECTRONICS

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SPEAr320S

Device functions

Doc ID 022508 Rev 2

25/113

Main features:

●

Supported cryptographic algorithms:

–

Advanced encryption standard (AES) cipher in ECB, CBC, CTR modes

–

Data encryption standard (DES) cipher in ECB and CBC modes

–

SHA-1, HMAC-SHA-1, MD5, HMAC-MD5 digests

●

Hardware chaining of cryptographic stages for optimized data flow when multiple

algorithms are required to process the same set of data (for example, encryption and

hashing on the fly)

2.25

System controller (SYSCTR)

The system controller provides an interface for controlling the operation of the overall

system.

Main features:

●

Power saving system mode control

●

Crystal oscillator and PLL control

●

Configuration of system response to interrupts

●

Reset status capture and soft reset generation

●

Watchdog and timer module clock enable

Using three mode control bits, the system controller switches the SPEAr320S to any of the

four different modes: DOZE, SLEEP, SLOW and NORMAL.

●

SLEEP mode: in this mode, the system clocks, HCLK and CLK, are disabled and the

system controller clock, SCLK, is driven by a low-speed oscillator (nominally

32768 Hz). When either a FIQ or an IRQ interrupt is generated (through the VIC), the

system enters DOZE mode. Additionally, the operating mode setting in the system

control register automatically changes from SLEEP to DOZE.

●

DOZE mode: in this mode, the system clocks, HCLK and CLK, and the system

controller clock are driven by a crystal oscillator (24 MHz) or a low-frequency oscillator

(32 KHz). The system controller moves into SLEEP mode from DOZE mode only when

none of the mode control bits are set and the processor is in wait-for-interrupt state. If

SLOW mode or NORMAL mode is required, the system moves into the XTAL control

transition state to initialize the crystal oscillator.

●

SLOW mode: during this mode, both the system clocks and the system controller clock

are driven by the crystal oscillator. If NORMAL mode is selected, the system goes into

the “PLL control” transition state. If neither the SLOW nor the NORMAL mode control

bits are set, the system goes into the “Switch from XTAL” transition state.

●

NORMAL mode: in NORMAL mode, both the system clocks and the system controller

clock are driven by the PLL output. If the NORMAL mode control bit is not set, then the

system goes into the “Switch from PLL” transition state.

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