SPEAR320S datasheet(16/113 Pages) STMICROELECTRONICS

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Device functions

SPEAr320S

16/113

Doc ID 022508 Rev 2

2.8

USB 2.0 Device port (UDC)

SPEAr320S provides a USB 2.0 Device port with integrated PHY.

Main features:

●

Support for all standard modes:

–

high-speed mode (USB 2.0, up to 480 Mbps)

–

full-speed mode (USB 1.1, up to 12 Mbps)

–

low-speed mode (USB 1.1, up to 1.5 Mbps)

●

Up to 16 physical endpoints, configurable as different logical endpoints

●

Internal 4 KB FIFO queue (shared among all the endpoints)

●

DMA mode, with descriptor-based structures in application memory

●

Slave-only mode

●

Support for 8-, 16- and 32-bit wide data transactions on the internal bus

●

Support for USB plug detection (UPD)

2.9

Fast Ethernet ports (MII/RMII)

SPEAr320S features three multiplexed Ethernet MACs, supporting up to two ports

concurrently.

The three controllers are named:

●

MII0

●

RMII0

●

MII1/RMII1

2.9.1

MII0 Ethernet controller

Main features:

●

Media independent interface (MII) to an external PHY as defined in the IEEE 802.3u

specification

●

Support for 10 and 100 Mbps data transfer rates

●

Support for both full-duplex and half-duplex (CSMA/CD protocol) operating modes

●

Integrated FIFO queues (4 KB RX, 2 KB TX)

●

Native DMA with single-channel transmit and receive engines, providing 32-/64-/128-bit

data transfers; DMA provides ring-buffer or linked-list descriptor options.

●

Programmable Ethernet frame length to support both standard and jumbo frames (with

size up to 16 KB)

●

Flexible address filtering modes

●

Statistics counter registers for RMON/MIB

●

Support for 802.1Q VLAN tagging

●

Wake-on-LAN support

●

Automatic padding and CRC generation on transmitted frames

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