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SPEAR320S 数据表(PDF) 64 Page - STMicroelectronics |
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SPEAR320S 数据表(HTML) 64 Page - STMicroelectronics |
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64 / 113 page  Pin description SPEAr320S 64/113 Doc ID 022508 Rev 2 MII1_RXD0 PHY receive data These bits provide the MII receive data nibble. The validity of the data is qualified with MII1_RXDV and MII1_RXER. I PL_GPIO_87/G13 2, Extended MII1_RXD1 PL_GPIO_86/E17 2, Extended MII1_RXD2 PL_GPIO_85/F15 2, Extended MII1_RXD3 PL_GPIO_84/D17 2, Extended MII1_RXDV PHY receive data valid When high, indicates that the data on the MII1_RXDn bus is valid. It remains asserted continuously from the first recovered byte/nibble of the frame through the final recovered byte/nibble. I PL_GPIO_89/F17 2, Extended MII1_RXER PHY receive error When high, indicates an error or carrier extension in the received frame on the MII1_RXDn bus. I PL_GPIO_88/F16 2, Extended MII1_TXCLK Transmission clock This is the transmission clock (25/2.5 MHz in 100M/10Mbps) provided by the external PHY for the MII. All the MII transmission signals generated by the MAC are synchronous to this clock. I PL_GPIO_97/H16 2, Extended MII1_TXD0 PHY transmit data. These bits provide the MII transmit data nibble. The validity of the data is qualified with MII1_TXEN and MII1_TXER. O PL_GPIO_96/H15 2, Extended MII1_TXD1 PL_GPIO_95/H14 2, Extended MII1_TXD2 PL_GPIO_94/H13 2, Extended MII1_TXD3 PL_GPIO_93/G17 2, Extended MII1_TXEN PHY transmit data enable When high, indicates that valid data is being transmitted on the MII1_TXDn bus. O PL_GPIO_92/G16 2, Extended MII1_TXER PHY transmit error When high, indicates a transmit error or carrier extension on the MII1_TXDn bus. O PL_GPIO_91/G15 2, Extended RMII0/RMII1 RMII_MDC Management data clock The MAC provides timing reference for the RMII_MDIO signal through this aperiodic clock. The maximum frequency of this clock is 2.5 MHz.This clock is generated from the application clock (HCLK) via a clock divider. O PL_GPIO_11/E5 Extended mode RMII_MDIO Management data input/output IO PL_GPIO_10/C3 Extended mode RMII_REF_CLK 50 MHz reference clock input for RMII interface I PL_GPIO_22/D6 Extended mode Table 31. Ethernet signals description (continued) Signal name Description Dir. PL_GPIO_# / ball number Configuration mode (see Section 3.4.2) |
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