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SPEAR320S 数据表(PDF) 89 Page - STMicroelectronics |
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SPEAR320S 数据表(HTML) 89 Page - STMicroelectronics |
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89 / 113 page  SPEAr320S Timing requirements Doc ID 022508 Rev 2 89/113 5.9 FSMC timing characteristics The FSMC present in SPEAr320S can interface external parallel NAND Flash memories. The timing characterization is performed using primetime assuming an output load capacitance of 3 pF on the data, 15 pF on FSMC_CSx, FSMC_RE and FSMC_WE and 10 pF on FSMC_ADDR_LE and FSMC_CMD_LE. Figure 22. Output command signal waveform Figure 23. Output address signal waveform Figure 24. In/out data address signal waveform FSMC_CS# FSMC_WE FSMC_D# Command tCLE tWE tIO FSMC_CMD_LE FSMC_ADDR_LE FSMC_CS# FSMC_WE FSMC_D# Address tALE tWE tIO FSMC_CS# FSMC_WE FSMC_D# (out) Data Out tIO FSMC_D# (in) FSMC_RE tRE -> IO tWE tRE tREAD tNFIO -> FFs |
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