LSM6DS3 datasheet(49/100 Pages) STMICROELECTRONICS

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DocID026899 Rev 8

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LSM6DS3

100

9.7

FIFO_CTRL5 (0Ah)

FIFO control register (r/w).

Table 34. FIFO_CTRL5 register description

Table 31. Fourth FIFO data set decimation setting

DEC_DS4_FIFO[2:0]

Configuration

000

Fourth FIFO data set not in FIFO

001

No decimation

010

Decimation with factor 2

011

Decimation with factor 3

100

Decimation with factor 4

101

Decimation with factor 8

110

Decimation with factor 16

111

Decimation with factor 32

Table 32. Third FIFO data set decimation setting

DEC_DS3_FIFO[2:0]

Configuration

000

Third FIFO data set not in FIFO

001

No decimation

010

Decimation with factor 2

011

Decimation with factor 3

100

Decimation with factor 4

101

Decimation with factor 8

110

Decimation with factor 16

111

Decimation with factor 32

Table 33. FIFO_CTRL5 register

0(1)

1. This bit must be set to ‘0’ for the correct operation of the device.

ODR_

FIFO_3

ODR_

FIFO_2

ODR_

FIFO_1

ODR_

FIFO_0

FIFO_

MODE_2

FIFO_

MODE_1

FIFO_

MODE_0

ODR_FIFO_[3:0]

FIFO ODR selection, setting FIFO_MODE also. Default: 0000

For the configuration setting, refer to Table 35

FIFO_MODE_[2:0]

FIFO mode selection bits, setting ODR_FIFO also. Default value: 000

For the configuration setting refer to Table 36

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