ST7MC1 datasheet(154/308 Pages) STMICROELECTRONICS

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MOTOR CONTROLLER (Cont’d)

10.6.6.6 Z Event Generation (BEMF Zero

Crossing)

When both C and D events have occurred, the

PWM may be switched to another group of outputs

(depending on the OS[2:0] bits in the MCRB regis-

ter) and the real BEMF zero crossing sampling can

start (see Figure 87). After Z event, the PWM can

also be switched to another group of outputs be-

fore the next C event.

A BEMF voltage is present on the non-powered

terminal but referred to the common star connec-

tion of the motor whose voltage is equal to VDD/2.

When a winding is free-wheeling (during PWM off-

time) its terminal voltage changes to the other

power rail voltage, this means if the PWM is ap-

plied on the high side driver, free-wheeling will be

done through the low side diode and the terminal

will be 0V.

This is used to force the common star connection

to 0V in order to read the BEMF referred to the

ground terminal.

Consequently, BEMF reading (i.e. comparison

with a voltage close to 0V) can only be done when

the PWM is applied on the high side drivers. When

the BEMF signal crosses the threshold voltage

close to zero, it is called a hardware zero-crossing

event ZH. A filter can be implemented on the ZH

event detection (see Figure 83).

The Z event filter register (MZFR) is used to select

the number of consecutive Z events needed to

generate the ZH event. Alternatively, the PZ bit

can be used to enable protection as described in

Figure 83. on page 156

For this reason the MTC outputs can be split in two

groups called LOW and HIGH and the BEMF read-

ing will be done only when PWM is applied on one

of these two groups. The REO bit in the MPOL

BEMF sensing (high side group). It has to be con-

figured whatever the sampling mode.

When enabled by the HZ bit in MCRC register, the

current value of the MTIM timer is captured in reg-

ister MZREG when this event occurs in order to be

able to compute the real delay in the delay manag-

er part for hardware commutation but also to be

able to simulate zero-crossing events for other

steps.

When enabled by the SZ bit set in the MCRC reg-

ister, a zero-crossing event can also be simulated

by comparing the MTIM timer value with the

MZREG register. This kind of zero-crossing event

is called simulated zero-crossing ZS.

If both HZ and SZ bits are set in MCRC register,

the first event that occurs, triggers a zero-crossing

event.

Depending on the edge and level selection (ZVD

and CPB) bits and when PWM is applied on the

correct group, a BEMF zero crossing detection (ei-

ther ZH or ZS) sets the ZI bit in the MISR register

and generates an interrupt if the ZIM bit is set in

the MIMR register.

Caution 1: Due to the alternate automatic capture

and compare of the MTIM timer with MZREG reg-

ister by ZH and ZS events, the MZREG register

should be manipulated with special care.

Caution 2: Due to the event generation protection

in the MZREG, MCOMP and MDREG registers for

Soft Event generation, the value written in the

MZREG register in simuated zero-crossing mode

(SZ=1) is checked by hardware after the D (either

DH or DS) event. If this value is less than or equal

to the MTIM counter value at this moment, the sim-

ulated zero-crossing event is generated immedi-

ately and the MTIM current value overwrites the

value in the MZREG register. See “Built-in Checks

and Controls for simulated events” on page 174.

The Z event also triggers some timer/multiplier op-

erations, for more details see Section 10.6.7

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