ST7MC1 datasheet(158/308 Pages) STMICROELECTRONICS

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ST7MC1/ST7MC2

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MOTOR CONTROLLER (Cont’d)

10.6.6.9 Sampling block

For a full digital solution, the phase comparator

output sampling frequency is the frequency of the

PWM signal applied to the switches and the sam-

pling for the Z event detection in sensorless mode

is done at the end of the off time of this PWM sig-

nal to avoid to have to re-create a virtual ground

because when the PWM signal is off, the star point

is at ground due to the free-wheeling diode. That’s

why, the sampling for Z event detection is done by

default during the OFF-state of the PWM signal

and therefore at the PWM frequency.

In current mode, this PWM signal is generated by

a combination of the output of the measurement

window generator (SA[3:0] bits), the output of the

current comparator and a minimum OFF time set

by the OT[3:0] bits for system stabilisation.

In voltage mode, this PWM signal is generated by

the 12-bit PWM generator signal in the compare U

the sampling is done at the end of the OFF time of

the PWM signal for system stabilisation. The PWM

signal is put OFF as soon as the current feedback

reaches the current input limitation. This can add

an OFF time to the one programmed with the 12-

bit Timer.

For D event detection in sensorless mode, no spe-

cific PWM configuration is needed and the sam-

pling frequency (fSCF, see Table 82) is completely

independent from the PWM signal.

In sensor mode, the D event detection is not need-

ed as the MCIA, MCIB and MCIC pins are the dig-

ital signals coming from the hall sensors so no

specific PWM configuration is needed and the

sampling for the Z detection event is done at

fSCF, completely independent from the PWM sig-

nal.

In sensorless mode, if a virtual ground is created

by the addition of an external circuit, sampling for

the Z event detection can be completely independ-

ent from the PWM signal applied to the switches.

Setting the SPLG bit in the MCRC register allows a

sampling frequency of fSCF for Z event detection

independent from the PWM signal after getting the

D (end of demagnetisation) event. This means that

the sampling order is given whatever the PWM

signal (during the ON time or the OFF time). As

soon as the SPLG bit is set in the MCRC register,

the minimum OFF time needed for the PWM signal

in current mode is set to 0µs and a true 100% duty

cycle can be set in the 12-bit PWM generator com-

pare register in voltage mode.

Specific applications can require sampling for the

Z event detection only during the ON time of the

PWM signal. This can happen when the PWM sig-

nal is applied only on the low side switches for Z

event detection. In this case, during the OFF time

of the PWM signal, the phase voltage is tied to the

application voltage V and no back-EMF signal can

be seen. During the ON time of the PWM signal,

the phase voltage can be compared to the neutral

point voltage and the Z event can be detected.

Therefore, it is possible to add a programmable

delay before sampling (which is normally done

when the PWM signal is switched ON) to perform

the sampling during the ON time of the PWM sig-

nal. This delay is set with the DS [3:0] bits in the

MCONF register.

Table 33. Delay length before sampling

Note: Times are indicated for 4 MHz fPERIPH

As soon as a delay is set in the DS[3:0] bits, the

minimum OFF time for the PWM signal is no long-

er required and it is automatically set to 0µs in cur-

rent mode in the internal sampling clock and a true

100% duty cycle can be set in the 12-bit PWM

generator compare U register if needed.

DS3

DS2

DS1

DS0

Delay added to

sample at Ton

000

No delay added.

Sample during

Toff

000

2.5 µs

001

5 µs

001

7.5 µs

010

10 µs

12.5 µs

011

15 µs

17.5 µs

100

20 µs

22.5 µs

101

25 µs

27.5 µs

110

µs

32.5

µs

111

µs

37.5

µs

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