AD6652BBC datasheet(45/76 Pages) AD

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AD6652

Rev. 0 | Page 45 of 76

ST (BIST)

self-

hich is intended to test the integrity of the high speed

ain

s feature provides a simple pass/fail test, which gives

el RAM is operational. Follow these

est:

t at

, the

3-Bi

Data MEM

USER-CONFIGURABLE BUILT-IN SELF-TE

The AD6652 includes two built-in test features to test the

integrity of each channel. The first is a RAM BIST (built-in

test), w

random access memory within the AD6652. The second is

channel BIST, which is designed to test the integrity of the m

signal paths of the AD6652. The BIST functions are independ-

ent of each other and can be operated simultaneously.

RAM BIST

Use the RAM BIST to validate functionality of the on-chip

RAM. Thi

confidence that the chann

steps to perform this t

Put the channels to be tested into sleep mode via the

External Address Register 0x01.

Program the RAM BIST enable bit in the RCF Register

0xA8 of the channel address registers to logic high. Wai

least 1600 clock cycles, then perform Step 3.

Read back Register 0xA8 (see Table 19). If Bit 0 is high

test is not yet complete. If Bit 0 is low, the test is complete

and Bits 1 and 2 indicate the condition of the internal

RAM. If Bit 1 is high, then CMEM is bad. If Bit 2 is high,

then DMEM is bad.

Table 19. BIST Register 0xA8

t Data

Coefficient MEM

xx1

Test incomplete

000

PASS

010

FAIL

PASS

100

PASS

FAIL

110

FAIL

CHANNEL BIST

The channel BIST is a thorough test of the selected AD6652

un to

tly.

nel 0 in sleep mode.

Configure the channels to be tested as required for the

application. This might require setting the NCO

parameters, the decimation rates, scalars, and RCF

coefficients.

Program the start hold-off counter, 0x83, to a value of 1 in

the channel address registers of the channels to be tested.

Program Channel Address Registers 0xA5 and 0xA6 to all

0s for the channels to be tested.

Enable the channel BIST located at 0xA7 by programming

Bits 19–0 to the number of RCF outputs to observe.

For External Address Register 5:3–0, program the desired

SYNC CH bits to logic high to select which channels will

receive a start soft-sync signal.

External Address Register 5:4 should be programmed high

to emit a one-shot soft sync pulse for the start function.

Reset External Address Register 5:6 to 0 to allow user-

provided test vectors. The internal pseudorandom number

generator can also be selected to generate a PN data input

sequence by setting Bit 7 high.

For External Address Register 5, an internal negative full-

scale sine wave is output at the NCO frequency, when Bit 6

is set to 1 and Bit 7 is cleared.

10. When the SOFT_SYNC control register is written with the

above parameters, the selected channels become active

with the programmed attributes.

11. If the user is providing external vectors, then the chip can

be brought out of sleep mode by one of the other methods.

12. After a sufficient amount of time, the channel BIST

Signature Registers 0xA5 and 0xA6 contain a numeric

value that can be compared to the expected value for a

known good AD6652 with the exact same configuration. If

the values are the same, then there is a very low probability

of an error in the channel.

Note: To better visualize these instructions, see Figure 53, Sync

Control Block Diagram; Table 22, the External Memory Map;

and Table 24, the Channel Address Registers Memory Map.

signal path. With this test mode enabled, it is possible to use

externally supplied test vectors or an internal pseudonoise (PN)

data generator. An error signature register in the RCF monitors

the output data of the channel and is used to determine if the

proper data exits the RCF. If errors are detected, then each

internal block can be bypassed and another test can be r

debug the fault. The I and Q paths are tested independen

Follow these steps to perform this test:

Place the channel(s) to be programmed in sleep mode at

External Address 3:3–0. Set the appropriate bits high.

Example 3:0 = 1 places Chan

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