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AD6652BBC 数据表(PDF) 9 Page - Analog Devices

部件名 AD6652BBC
功能描述  12-Bit, 65 MSPS IF to Baseband Diversity Receiver
PDF  76 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD6652BBC 数据表(HTML) 9 Page - Analog Devices

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AD6652
Rev. 0 | Page 9 of 76
MICROPROCESSOR PORT TIMING CHARACTERISTICS
All timing specifications valid over VDD range of 2.25 V to 2.75 V and VDDIO range of 3.0 V to 3.6 V.
CLOAD = 40 pF on all outputs, unless otherwise specified.
Table 7.
MICROPROCESSOR PORT, MODE INM (MODE = 0)
Temp
Test Level
Min
Typ
Max
Unit
MODE INM WRITE TIMING
tSC
Control1 to
↑CLK Setup Time
Full
IV
2.0
ns
tHC
Control1 to
↑CLK Hold Time
Full
IV
2.5
ns
tHWR
WR(R/W) to RDY(DTACK) Hold Time
Full
IV
7.0
ns
tSAM
Address/Data to WR(R/W) Setup Time
Full
IV
3.0
ns
tHAM
Address/Data to RDY(DTACK) Hold Time
Full
IV
5.0
ns
tDRDY
WR(R/W) to RDY(DTACK) Delay
Full
IV
8.0
ns
tACC
WR(R/W) to RDY(DTACK) High Delay
Full
IV
4 × tCLK
5 × tCLK
9 × tCLK
ns
MODE INM READ TIMING
tSC
Control1 to
↑CLK Setup Time
Full
IV
5.0
ns
tHC
Control1 to
↑CLK Hold Time
Full
IV
2.0
ns
tSAM
Address to RD(DS) Setup Time
Full
IV
0.0
ns
tHAM
Address to Data Hold Time
Full
IV
5.0
ns
tDRDY
RD(DS) to RDY(DTACK) Delay
Full
IV
8.0
ns
tACC
RD(DS) to RDY(DTACK) High Delay
Full
IV
8 × tCLK
10 × tCLK
13 × tCLK
ns
MICROPROCESSOR PORT, MODE MNM (MODE = 1)
Temp
Test Level
Min
Typ
Max
Unit
MODE MNM WRITE TIMING
tSC
Control1 to
↑CLK Setup Time
Full
IV
2.0
ns
tHC
Control1 to
↑CLK Hold Time
Full
IV
2.5
ns
tHDS
DS(RD) to DTACK(RDY) Hold Time
Full
IV
8.0
ns
tHRW
R/W(WR) to DTACK(RDY) Hold Time
Full
IV
7.0
ns
tSAM
Address/Data To R/W(WR) Setup Time
Full
IV
3.0
ns
tHAM
Address/Data to R/W(WR) Hold Time
Full
IV
5.0
ns
tDDTACK
DS(RD) to DTACK(RDY) Delay
Full
IV
8.0
ns
tACC
R/W(WR) to DTACK(RDY) Low Delay
Full
IV
4 × tCLK
5 × tCLK
9 × tCLK
ns
MODE MNM READ TIMING
tSC
Control1 to
↑CLK Setup Time
Full
IV
5.0
ns
tHC
Control1 to
↑CLK Hold Time
Full
IV
2.0
ns
tHDS
DS(RD) to DTACK(RDY) Hold Time
Full
IV
8.0
ns
tSAM
Address to DS(RD) Setup Time
Full
IV
0.0
ns
tHAM
Address to Data Hold Time
Full
IV
5.0
ns
tDDTACK
DS(RD) to DTACK(RDY) Delay
Full
IV
8.0
ns
tACC
DS(RD) to DTACK(RDY) Low Delay
Full
IV
8 × tCLK
10 × tCLK
13 × tCLK
ns
1 Specification pertains to control signals: R/W, (WR), DS, (RD), and CS.



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