AD6652BBC datasheet(63/76 Pages) AD

63 / 76 page

AD6652

Rev. 0 | Page 63 of 76

t po

ble variou

late

ures used p

trol. Dep

g on the

ode of operation, up to four different signal paths can be

onitored with these registers. These features are accessed by

etting Bit 5 of External Address 3 (sleep regi

nd then

g the CAR (External Address 6) to address the eight

cations ava lable. Response to these settings is directed to

LIA

INPUT PORT CONTROL REGISTERS

The i

eat

npu

rt control registers ena

rimarily for level con

s i

ndin

nput-re

ster) a

usin

the

LIA,

, LIB, and LIB pins.

To access the input port registers, the progra

gain contro

ld be wr ten high. The CAR is then wri en with the

ess to th

orrect input port register.

ord is 10 bits wide and maps to the 10 MSB of the

antissa. If the upper 10 bits of Input Port A are less than o

ual to this alue, then the lower threshold

s been met. I

ormal chip peration, this starts the dwell time counter. If he

put signal increases above this value, then t e counter is

eloaded an awaits the input to drop back t

his level.

ord is 10 bits wide and maps to the 10 MSB of the

antissa. If t e upper 10 bits of Input Port A re greater th

ual to this alue, then the upper threshold as been met.

ormal chip peration, this causes the appro iate LI pin (LIA

LIA

l bit

shou

addr

e c

0x00: Lower Threshold A

This w

o t

0x01: Upper Threshold A

This w

an o

) to become active.

his word sets the time that the input signal must be at or

wer th

s deac

ed. For the

t level d

ell time m t be set to a

t 1. If set

s are disable

his is a 20

ster. Wh

old is met fol

ing an

ursion in

, the dwel

e counter i

ed and

cles as long

e input is a or below the lower threshold. I

e signal

eases ab

coun

eloaded

s for the

er th

old again.

in Range A Control Register

it 4 determ es the polarity of LIA and LIA

0x02: Dwell Time A

belo

the lo

reshold before the LI pin i

tivat

inpu

etector to work, the dw

leas

to 0, the LI function

d. T

-bit

regi

en the lower thresh

low

exc

to the upper threshold

l tim

load

begins to count high speed clo

f th

incr

ove the lower threshold, the

ter is r

and

wait

signal to fall below the l

res

0x03: Ga

. If this bit is

lear, then t

LI signal is high when the up r threshold has

een exceed . However, if this bit is set, the LI pin is low

hen active. his allows maximum flexibility hen using

is function

it 3 = 0 (Re

ved).

Bit 2–0 determines the internal latency of the gain detect

function. When the LIA, LIA

ser

pins are made active, they are

used to change an attenuator or gain stage. Because

DC, there is a latency associated with the

e settling of the gain change. This register

delay of the LIA, LIA

typically

this is prior to the A

DC and with th

llows the internal

signal to be

wer Threshold B

is 10 bits wide and maps to the 10 MSB of the

er 10 bits of Input Port B are less than or

e, then the lower threshold has been met. In

peration, this starts the dwell time counter. If the

al increases above this value, then the counter is

aits the input to drop back to this level.

0x05: Upper Threshold B

This w rd is 10 bits wide and maps to the 10 MSB of the

. If the upper 10 bits of Input Port B are greater than or

is value, then the upper threshold has been met. In

ip operation, this causes the appropriate LI pin (LIB

rogrammed.

0x04: Lo

This word

mantissa. If the upp

qual to this valu

ormal chip o

input sign

reloaded and aw

antissa

qual to th

ormal ch

LIB) to become active

0x06: Dwell Time B

d sets the time that the input signal must be at or below

pin is deactivated. For the

e dwell time must be set to at

1. If set to 0, the LI functions are disabled. This is a 20-bit

. When the lower threshold is met following an

into the upper threshold, the dwell time counter is

aded and begins to count high speed clock cycles as long as

is at or below the lower threshold. If the signal

aded and

he signal to fall below the lower threshold again.

ain Range B Control Register

e polarity of LIB and LIB

This wor

he lower threshold before the LI

nput level detector to work, th

least

excursion

the input

increases above the lower threshold, the counter is relo

waits for t

0x0: G

Bit 4 determines th

. If this bit is

h when the upper threshold has

, if this bit is set, the LI pin is low

is allows maximum flexibility when using

(Reserved.

etermines the internal latency of the gain detect

. When the LIB, LIB

clear, then the LI signal is hig

However

been exceeded.

when active. Th

this function.

it 3 = 0

it 2–0 d

unction

pins are made active, they are

sed to change an attenuator or gain stage. Because

r to the ADC, there is a latency associated with

nd with the settling of the gain change. This

llows the internal delay of the LIB, LIB

ypically u

his is prio

he ADC a

signal to

be programmed.

AD6652BBC 数据表(PDF) 63 Page - Analog Devices

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