AD6652BBC datasheet(60/76 Pages) AD

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AD6652

Rev. 0 | Page 60 of 76

Bit Wid

Channel Address

Comments

RCF Control Register

10:

RCF bypass BIST

RCF input select (own 0, other 1)

Program RAM bank 1/0

Use common exponent

Force output scale

5-4:

Output format

nt 12 + 4

1x: Floating poi

point 8 + 4

01: Floating

00: Fixed point

3-0:

Output scale

BIST Signature for I Path

BIST-I

BIST Signature for Q Path

BIST-Q

BIST Outputs to Accumulate

19-0:

Number of outputs (counter value read)

RAM BIST Control Register

D-RAM fail/pass

pass

C-RAM fail/

RAM BIST enable

Output Control Register

Map RCF data to BIST registers

Output format

1: 16-bit I and 16-bit Q

I and 12-bit Q

0: 12-bit

4-0:

Reserved, write to Logic 0

0x87: NCO Phase Offset Register

This register represents a 16-bit phase offset to the NCO. It can

be interpreted as values ranging from 0 to just under 2π. The

o the 16 MSBs of the 32-bit NCO

rrive at the final phase angle number

ular

16-bit phase offset is added t

phase accumulator to a

used to compute the amplitude value.

0x88: NCO Control Register

This 9-bit register controls features of the NCO and the

channel. The bits are defined in this section. For details, see the

Numerically Controlled Oscillator section.

Bits 8–7 of this register choose which one of the four

Pin_SYNC pins (A, B, C, or D) is used by the channel to initiate

channel start and frequency hop functions. These bits can also

be used to make timing adjustments to a channel.

Table 25 shows the bit logic state needed to select a partic

Pin_Sync.

Table 25. Bit Logic States for Sync Pins

0x88:8

0x88:7

Sync Pin Selected

Bit 6 of this register defines which ADC channel, A or B, is used

by the DDC channel being programmed. If this bit is low, then

nput Port A selected; if this bit is high, Input Port B is selected.

Bits 5–4 are reserved and must be written logic low.

ared.

equen-

e and amplitude dither

use of these features is

stage

to be bypassed. When this occurs, the data from Input Port A is

th of the channel and the data from Input

ws a

lue

ister is the decimation minus one. The rCIC2

ecimation can range from 1 to 4096, depending upon the

interpolation of the channel. The decimation must always be

greater than the interpolation.

Bit 3 determines whether or not the phase accumulator of th

NCO is cleared when a hop occurs. The hop can originate fro

either Pin_SYNC or Soft_SYNC. When this bit is set to 0, the

hop is phase-continuous and the accumulator is not cle

When this bit is set to 1, the accumulator is cleared to 0 before

begins accumulating the new frequency word. This is appropri

ate when multiple channels are hopping from different fr

cies to a common frequency.

Bits 2–1 control whether or not the phas

functions of the NCO are activated. The

determined by the system constraints. See the Numericall

Controlled Oscillator section for more information on the use

of dither. As usual, a logic high activates the function.

Bit 0 of this register allows the NCO frequency translation

passed down the I pa

Port B is passed down the Q path of the channel. This allo

real filter to be performed on baseband I and Q data.

Ox89–0x8F: Unused

Unused.

0x90: rCIC2 Decimation − 1 (MrCIC2 − 1)

This register sets the decimation in the rCIC2 filter. The va

written to this reg

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