AD6652BBC datasheet(46/76 Pages) AD

46 / 76 page

AD6652

Rev. 0 | Page 46 of 76

P SYNCHRONIZATION

dated using the versatile

soft-sync and pin-sync signals normally associated with

g sections. The synchronization is

shad

can

ia the microport), or a

Pin_Sync (via any of the four AD6652 SYNC pins A, B, C, and

for a

CHANNEL/CHI

The AD6652 has been designed to easily synchronize two

common functions: Start and Hop. While the AGC stage can

also be synchronized, it is not accommo

AD6652 synchronization. Start and Hop functions are describe

in detail in the followin

acco plished with the use of a shadow register and a hold-off

counter. See Figure 52 for a simplified schematic of the NCO

ow register and NCO frequency hold-off counter to

understand basic operation. Triggering of the hold-off counter

occur with either a Soft_Sync (v

D). igure 53 details how synchronization signals are managed

single receive processing channel.

READBACK

ENB

NCO HOP

HOLD-OFF

COUNTER

NCO

SHADOW

Q31

NCO

FREQUENCY

D31

Q31

SOFT SYNC

PIN SYNC

FROM

0x85 AND

0x86 NCO

FREQUENCY

TO NCO

PHASE

ACCUMULATOR

D31

D15

CLK

PRELOAD

INPUTS FROM

0x84

FROM TC OF

START HOLD-OFF

COUNTER

Figure 52. NCO Shadow Register and Hold-Off Counter

There are two types of synchronization stimuli to choose from:

Soft_Sync and Pin_Sync. The first method is initiated over the

microport or serial programming port using a software routine.

The second method relies on an external stimulus that is

attached to one of the four synchronization input pins (SYNC

A, B, C, and D). In both cases, a logic high triggers the synchro-

nization process. Both methods can be used simultaneously by

setting the appropriate qualifiers.

START

Start refers to the startup of an individual channel or chip, or

multiple chips. If a channel is not used, it should be placed in

sleep mode to reduce power dissipation. Following a hard reset

(low pulse on the AD6652 RESET pin), all channels are placed

in sleep mode. Channels can also be manually placed in sleep

he start

lue is 0, this defeats the start function, and the

ontrol section).

What happens if a Start_Sync pulse is received while the

channel is awake (actively processing data)? This can actually be

a very useful tool to dynamically adjust the RCF phase or

timing to allow synchronization of multiple AD6652 ICs. Refer

to the discussions of Registers 0x83 and 0xA1 in the Channel

Address Register (CAR) section for further explanation.

Start with No Sync

If no synchronization is needed to start multiple channels or

multiple AD6652s, use the following method to initialize the

device:

To program a channel, put it in sleep mode (bit high,

External Address 3:3–0), then load all appropriate control

and memory registers to set up the proper channel

configuration.

Load the start hold-off counter (0x83) with a 16-bit value

from 1 to 216 − 1.

Set the channel’s sleep bit low (External Address 3:3–0).

Awakening from sleep involves an internally generated

start command that performs the same functions as a

software-generated sync pulse. This activates the channel

after the hold-off counter reaches a value of one with the

newly programmed or previous parameters.

mode by writing to the register controlling the sleep function,

External Address 3:3–0.

Before and after a start command is received by one or more

channels, the following occurs:

Just before the start command is issued, while the channel i

in sleep mode, any or all control registers, including filter

coefficients, can be safely reprogrammed without crashin

the AD6652 or creating unwanted output.

When a Start_Sync pulse is received, it transfers the

contents of the channel’s start hold-off register, 0x83, to the

counter’s preload inputs and commences counting. When

the count reaches a value of one, the channel is awakened

and initialized with the information from each applicab

preload va

channel remains dormant.

Note that start does not affect the AGC hold-off counter. The

counter can be triggered only by setting the sync now bit or by

pin sync signals (see the Automatic Gain C

AD6652BBC 数据表(PDF) 46 Page - Analog Devices

AD6652BBC 数据表(HTML) 46 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76

数据表下载