AD6652BBC datasheet(68/76 Pages) AD

68 / 76 page

AD6652

Rev. 0 | Page 68 of 76

Bit Width

Comments

Address

Channel data interleaved

2-channel mode/separate AB

4-channel mode/AB same port

AGC_CH select

Data comes from AGCs

Data comes from channels

Port Clock Control

2–1:

PCLK divisor

PCLK master/slave2

Slave

Master

1 Set the LHB A and/or LHB B enable bits to logic low only when the entire block functions

functions) are to be

shut down.

2 PCLK boots as a slave.

0x0E: AGC A Loop Gain

This 8-bit register defines the open loop gain K. Its value can be

set from 0 to 0.996 in steps of 0.0039. This value of K is updated

in the AGC loop each time the AGC is initialized.

0x0F: AGC A Pole Location

This 8-bit register defines the open loop filter pole location P. Its

0 to 0.996 in steps of 0.0039. This value of

umber of samples to be averaged before

IC decimating filter. This number can be

ean-

utput word length of the AGC. The output

word can be 4 to 8, 10, 12, or 16 bits wide. The control register

bit representation to obtain different output word lengths is

given in Table 29.

Bit 4 of this register sets the mode of operation for the AGC.

When this bit is 0, the AGC tracks to maintain the output signal

level; when this bit is 1, the AGC tracks to maintain a constant

clipping error. See the Automatic Gain Control section for

details about these two modes.

Bits 3–1 are used to configure the synchronization of the AGC.

The CIC decimator filter in the AGC can be indirectly

synchronized to an externally generated signal. When synchro-

nized, the AGC outputs an update sample for the AGC error

calculation and filtering. This way, the AGC gain changes can be

synchronized to a Rake receiver or other external block.

Note: The hold-off counter of AGC B shares the pin sync

fore, if the user

intends to use the AGC B’s hold-off counter, the user must

attach the external sync signal to the pin sync that will be

assigned to DDC Channel 2. The hold-off counter must be

programmed with a 16-bit number that corresponds to the

desired delay before a new CIC decimated value is updated.

Writing a logic high to the proper pin sync pin triggers the AGC

hold-off counter with a retriggerable one-shot pulse every time

the pin is written high.

Bit 3 is the sync now bit. If the user chooses not to use pin sync

signals, the user can use the Sync Now command by program-

ming this bit high. This performs an immediate start of

not

lize on

gain K, and pole parameter P

are loaded. When Bit 2 = 0, the above-mentioned parameters are

not updated and the CIC filter is not cleared. In both cases, an

AGC update sample is output from the CIC filter and the

decimator starts operating towards the next output sample

whenever a Sync Now occurs.

Bit 1 is used to ignore repetitive Pin_Sync signals. In some

applications, the synchronization signal might occur periodi-

cally. If this bit is clear, each Pin_Sync resynchronizes the AGC.

(LHB signal interleaving, LHB filtering, and AGC

value can be set from

P is updated in the AGC loop each time the AGC is initialized.

This open loop pole location directly impacts the closed loop

pole locations. See the Automatic Gain Control section.

0x10: AGC A Average Samples

This 6-bit register contains the scale used for the CIC filter and

the number of power samples to be averaged before being fed t

the CIC filter.

Bits 5–2 define the scale used for the CIC filter.

Bits 1–0 define the n

they are sent to the C

set between 1 and 4 with 00 meaning one sample and 11 m

ing four samples.

0x11: AGC A Update Decimation

This 12-bit register sets the AGC decimation ratio from 1 t

4096. Set an appropriate scaling factor to avoid loss of bits.

0x12: AGC B Control Register

Bits 7–5 define the o

assigned to DDC processing Channel 2. There

decimation for a new update sample and initializes the AGC, if

Bit 2 is set. This bit has a one-shot characteristic and does

need to be reset in order to respond to a new logic high being

written to it. Use of the sync now bit bypasses the AGC hold-off

counters; therefore, the name Sync Now.

Bit 2 is used to determine whether the AGC should initia

a Sync Now or not. When this bit is set, the CIC filter is cleared

and new values for CIC decimation, number of averaging

samples, CIC scale, signal gain Gs,

AD6652BBC 数据表(PDF) 68 Page - Analog Devices

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