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AD6652BBC 数据表(PDF) 8 Page - Analog Devices |
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AD6652BBC 数据表(HTML) 8 Page - Analog Devices |
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8 / 76 page  AD6652 Rev. 0 | Page 8 of 76 GENERAL TIMING CHARACTERISTICS All timing specifications valid over VDD range of 2.25 V to 2.75 V and VDDIO range of 3.0 V to 3.6 V. CLOAD = 40 pF on all outputs, unless otherwise specified. Table 6. Parameter (Conditions) Temp Test Level Min Typ Max Unit CLK TIMING REQUIREMENTS tCLK CLK Period Full IV 15.4 ns tCLKL CLK Width Low Full IV 6.2 tCLK/2 ns tCLKH CLK Width High Full IV 6.2 tCLK/2 ns RESET TIMING REQUIREMENTS tRESL RESET Width Low Full IV 30.0 ns LEVEL INDICATOR OUTPUT SWITCHING CHARACTERISTICS tDLI ↑CLK to LI (LIA, LIA; LIB, LIB) Output Delay Time Full IV 3.3 10.0 ns SYNC TIMING REQUIREMENTS tSS SYNC(A,B,C,D) to ↑CLK Setup Time Full IV 2.0 ns tHS SYNC(A,B,C,D) to ↑CLK Hold Time Full IV 1.0 ns PARALLEL PORT TIMING REQUIREMENTS (MASTER MODE) Switching Characteristics1 tDPOCLKL ↓CLK to ↑PCLK Delay (Divide-by-1) Full IV 6.5 10.5 ns tDPOCLKLL ↓CLK to ↑PCLK Delay (Divide-by-2, -4, or -8) Full IV 8.3 14.6 ns tDPREQ ↑PCLK to ↑PxREQ Delay 1.0 ns tDPP ↑PCLK to Px[15:0] Delay 0.0 ns Input Characteristics tSPA PxACK to ↓PCLK Setup Time 7.0 ns tHPA PxACK to ↓PCLK Hold Time −3.0 ns PARALLEL PORT TIMING REQUIREMENTS (SLAVE MODE) Switching Characteristics1 tPOCLK PCLK Period Full IV 12.5 ns tPOCLKL PCLK Low Period (when PCLK Divisor = 1) Full IV 2.0 0.5 × tPOCLK ns tPOCLKH PCLK High Period (when PCLK Divisor = 1) Full IV 2.0 0.5 × tPOCLK ns tDPREQ ↑PCLK to ↑PxREQ Delay 10.0 ns tDPP ↑PCLK to Px[15:0] Delay 11.0 ns Input Characteristics tSPA PxACK to ↓PCLK Setup Time IV 1.0 ns tHPA PxACK to ↓PCLK Hold Time IV 1.0 ns LINK PORT TIMING REQUIREMENTS Switching Characteristics1 tRDLCLK ↑PCLK to ↑LxCLKOUT Delay Full IV 2.5 ns tFDLCLK ↓PCLK to ↓LxCLKOUT Delay Full IV 0 ns tRLCLKDAT ↑LCLKOUT to Lx[7:0] Delay Full IV 0 2.9 ns tFLCLKDAT ↓LCLKOUT to Lx[7:0] Delay Full IV 0 2.2 ns 1 The timing parameters for Px[15:0], PxREQ, and PxACK apply for Port A and B (x stands for A or B). |
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